SM8213AM datasheet(13/33 Pages) NPC

13 / 33 page

SM8213AM

NIPPON PRECISION CIRCUITS—13

Lock mode (dummy address setting is disabled)

If the sync code is detected during the preamble

period, device operation transfers to lock mode and

BS1 goes LOW. BS1 then goes HIGH again under

frame timing, where the frame number is set by ﬂags

FF0 to FF2, and the 28 addresses are compared with

ID-ROM (If the frame number is 0, BS1 stays

HIGH). If errors of 2 bits or less occur, the address is

still recognized. Since there are two code words per

frame, this check is done twice.

When one of the 28 addresses does not match, BS1

goes LOW and the device waits for the next frame or

sync code receive timing. If the sync code is still not

detected after two consecutive attempts, device oper-

ation transfers to idle mode, except during message

reception where operation stays in lock mode. If the

sync code is not detected on the second attempt, but

instead a pattern forming a preamble is detected,

device operation transfers to preamble mode and not

idle mode (preamble mode is more advantageous for

sync code detection).

When one of the 28 addresses does match, ATTN

goes LOW and the 32-address information (see

“Data/Flags” section) is transmitted to the CPU on

SDO in sync with the SCK clock.

When the address information is conﬁrmed to be a

message, BS1 is held HIGH and the message is

received. The received message is stored in a buffer

32-bit

error-corrected

information

(see

“Data/Flags” section), then ATTN goes LOW and

the data is transmitted to the CPU on SDO in sync

with the SCK clock.

When the address and message is received, ATTN

should be held LOW while the data is output on

SDO.

When an incoming message spans two or more

batches, additional sync code detection occurs dur-

ing sync code receive timing.

Message reception can be selected to end when

either an address code or idle code is detected, or

when interrupted using the decoder set command

BREAK input. This selection is made when setting

parameters that will not cause the message to termi-

nate. If the BREAK mode is selected, even if an

address other than the self address (MSB = 0) is

received during message reception, reception contin-

ues without interruption and address data is sent to

the microcontroller using the same data handling as

for a message. In this case, reception can only be

interrupted by a BREAK input signal from the

microcontroller.

In either of the above cases, message reception ends

if an end-of-message signal is sent. Note that if the

device address is received, the end-of-message data

is not transmitted.

When message reception ends, BS1 goes LOW and

the device waits for either the address detect timing

of the next frame or the sync code receive timing.

When sending data from the decoder to the micro-

controller, the SCK clock frequency should not be

less than 512, (1200), [2400] Hz. If this occurs, the

SCK counter is reinitialized. This function, however,

does make restoring operation easy even if this or

another clock is accidentally input.

Figure 7. Operating mode transition diagram

PREAMBLE

Mode

LOCK

Mode

IDLE

Mode

POWER-ON

Mode

A: After reset, parameters/addresses are set and start command

is issued.

B: Rate error or, within a fixed period, preamble pattern/sync

code not detected.

C: Preamble pattern detected.

D: Sync code detected 1 cycle immediately after transfer from

lock mode.

E: Sync code not detected on 2 consecutive attempts

F: Same as E, but preamble detected on the second attempt.

G: Sync code detected.

H: Parameters/addresses are set and start command is issued

from preamble/idle/lock mode.

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