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SM8213AM Arkusz danych(PDF) 19 Page - Nippon Precision Circuits Inc

Numer części SM8213AM
Szczegółowy opis  POCSAG Decoder For Multiframe Pagers
PDF  33 Pages
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Producent  NPC [Nippon Precision Circuits Inc]
Strona internetowa  http://www.npc.co.jp/en
Logo NPC - Nippon Precision Circuits Inc

SM8213AM Arkusz danych(HTML) 19 Page - Nippon Precision Circuits Inc

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SM8213AM
NIPPON PRECISION CIRCUITS—19
Decoder Internal Status Transfer (SM8213AM to CPU)
In the SM8213AM, the internal decoder status and
parameter/address end-of-processing confirmation,
is transmitted to the CPU. The microcontroller uses
this status information only when needed.
This is a 2-byte (16 bits) command where the first
byte is a decoder set read command and the second
byte is the decoder internal status that is sent to the
microcontroller in sync with the SCK clock.
The microcontroller can use this function when not
receiving data from the decoder (when ATTN is
HIGH only).
Note the following points when setting the read com-
mand:
s
When ATTN is HIGH
After data is transferred and until ATTN goes
LOW for the next transmit ready data signal, the
series processing should be such that it takes less
than {32
× (bit rate)} time. If it takes longer than
this amount of time, the command setting may be
delayed (relative to normal operation) when ATTN
goes LOW. Note that during this time, there is no
guarantee of data.
When ATTN goes HIGH (excluding write mode),
SCK is examined to determine if the signal is a
break, back-up, write or read command. During mes-
sage reception, ATTN is temporarily held HIGH if a
command is issued to set ATTN LOW. This delay
ensures that the data from the decoder is not misin-
terpreted. And in this case, even if ATTN keeps
LOW, transmitted receiving data is unstable.
Figure 11. Internal status transfer timing
ATTN
SCK
SDO
SDI
:
8-bit
× 2-byte = 16-bit unit time clock
:
8-bit
× 1-byte = 8-bit unit time data
:
8-bit
× 1-byte = 8-bit unit time indeterminate data
READ
STATUS DATA
Refer to the AC Characteristics section for detailed timing specifications.
Indicates indeterminate data output.
When the CPU interprets the internal status,
these portions can be ignored (discarded).



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