© 2013 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FAN53541 • Rev. 1.0.2

10

Operation Description

The FAN53541 is a step-down switching voltage regulator

that delivers an adjustable output from an input voltage

supply of 2.7 V to 5.5 V. Using a proprietary architecture with

synchronous rectification, the FAN53541 is capable of

delivering up to 5 A at over 90% efficiency. The regulator

operates at a nominal frequency of 2.4 MHz at full load,

which reduces the value of the external components to

470 nH for the output inductor and 20 µF for the output

capacitor. High efficiency is maintained at light load with

single-pulse PFM Mode.

Control Scheme

The

FAN53541

uses

a

proprietary

non-linear,

fixed-

frequency PWM modulator to deliver very fast load transient

response, while maintaining a constant switching frequency

over a wide range of operating conditions.

Regulator

performance

is

independent

of

the

output

capacitor ESR, allowing for the use of ceramic output

capacitors. Although this type of operation normally results in

a switching frequency that varies with input voltage and load

current, an internal frequency loop holds the switching

frequency constant over a large range of input voltages and

load currents.

For

very

light

loads,

the

FAN53541

operates

in

Discontinuous Current (DCM) single-pulse PFM Mode, which

produces low output ripple compared with other PFM

architectures.

Transition

between

PWM

and

PFM

is

transition between DCM and CCM Modes.

PFM Mode is disabled by holding the MODE pin HIGH. The

IC synchronizes to the MODE pin frequency. When

synchronizing to the MODE pin, PFM Mode is disabled.

Setting Output Voltage

(1)

R1 must be set at or below 100

KΩ; therefore:

(2)

Enable and Soft-Start

When the EN pin is LOW, the IC is shut down, all internal

circuits are off, and the part draws very little current. Raising

EN above its threshold voltage activates the part and starts

the soft-start cycle. During soft-start,

the modulator’s internal

reference is ramped slowly to minimize surge currents on the

input and prevents overshoot of the output voltage.

If large values of output capacitance are used, the regulator

1.2 ms from the beginning of soft-start, the regulator shuts

down and waits 1.6 ms before attempting a restart. If the

regulator is in current limit for 16 consecutive PWM cycles,

the regulator shuts down before restarting 1.6 ms later. This

applied during the startup.

a heavy constant-current load is approximately:

(3)

the load current during soft-start, expressed in A.

Diode Emulation Mode is employed during soft-start,

allowing the IC to start into a pre-charged output. Diode

emulation prohibits reverse inductor current from flowing

through the synchronous rectifier.

When EN is LOW, a 150

 resistor discharges V

Under-Voltage Lockout (UVLO)

When EN is HIGH, the under-voltage lockout keeps the part

from operating until the input supply voltage rises high

enough to operate properly. This ensures no misbehavior of

the regulator during startup or shutdown.

Input Over-Voltage Protection (OVP)

switching to protect the circuitry from excessive internal

voltage spikes. An internal filter prevents the circuit from

Current Limiting

A heavy load or short circuit on the output causes the current

in the inductor to increase until a maximum current threshold

is reached in the high-side switch. Upon reaching this point,

the high-side switch turns off, preventing high currents from

causing damage. 16 consecutive PWM cycles in current limit

cause the regulator to shut down and stay off for about

1.6 ms before attempting a restart.

In the event of a short circuit, the soft-start circuit attempts to

restart

and

produces

an

over-current

fault

after

16

consecutive cycles in current limit, which results in a duty

cycle of less than 5%, providing current into a short circuit.

External Frequency Synchronization

Logic 1 on the MODE pin forces the IC to stay in PWM

Mode. Logic 0 allows the IC to automatically switch to PFM

during light loads. If the MODE pin is toggled, the converter

synchronizes its switching frequency to four times the

The MODE pin is internally buffered with a Schmitt trigger,

which allows the MODE pin to be driven with slow rise and

fall

times.

An

asymmetric

duty

cycle

for

frequency

synchronization is permitted, provided it is consistent with

parametric table limits.

REF

REF

OUT

V

V

V

2

R

1

R









8

.

0

V

8

.

0

1

R

2

R









OUT

LOAD

OUT

V

800

I

8

.

5

C

MAX





