ADL5246ACPZN-R7 datasheet(23/36 Pages) AD

23 / 36 page

Data Sheet

ADL5246

Rev. A | Page 23 of 36

THEORY OF OPERATION

BASIC CONNECTIONS

The basic connections for operating the ADL5246 are shown in

Figure 74. The schematic of AMP3 is configured for operation

at 2.2 GHz.

Amplifier 1 (AMP1)

AMP1 in the ADL5246 is a broadband low noise amplifier. The

radio frequency (RF) input is internally matched to 50 Ω and

optimally matched for the minimum noise figure and is

unconditionally stable. The RF output is internally matched for 50

Ω. The RF inputs and outputs require dc blocking capacitors (C8

and C9) for operation. DC bias is supplied through Inductor L1

and is connected to the RFOUT1 pin. Three decoupling capacitors

(C40, C41, and C5) prevent RF signals from propagating on the dc

supply lines. The value of L1 must be high enough to isolate the

bias from RF; however, the exact value is not critical for operation.

The self resonance of L1 has little effect upon the operation of

AMP1, within reasonable limits. AMP1 is completely independent

from the rest of the ADL5246 and may be left unpowered if not

needed. When AMP1 is not in use, terminate the RFIN1 and

RFOUT1 pins to ground via a 100 pF capacitor and a 50 Ω

resistor in series on each pin.

Amplifier 2 (AMP2)

AMP2 is a 50 Ω internally matched RF VGA consisting of two

VVAs with an LNA in between them. RFIN2 and RFOUT2 are

internally ac-coupled with a 20 pF on-chip capacitor. The LNA

has an integral bypass switch that allows the user to choose

between a low gain range and a high gain range. When the LNA is

bypassed, it is also not powered, reducing the supply current by

approximately 59 mA.

Each VVA may be controlled independently or in tandem via

VGAIN1 and VGAIN2. Bias is supplied to AMP2 via VPOS1 and

VPOS2. VPOS1 provides the bias to the amplifier circuit, and

VPOS2 provides bias to the VVAs. Therefore, both VPOS1 and

VPOS2 must be connected to bias to operate AMP2.

Inductors L2 and L3 with capacitors C2, C4, C7, C16, C17, and

C20 prevent RF signals from propagating on the dc supply lines.

The L2 value has some bearing on the gain of AMP2, with the

10 nH value giving an unhindered frequency response as low as

approximately 0.6 GHz.

AMP2 is sensitive to capacitance on the VPOS2 bias line. Place all

bypass capacitors as shown in Figure 74. Excessive capacitance

between L3 and Pin 28 (VPOS2) can cause undesirable gain loss.

When AMP2 is not in use, terminate the RFIN2 and RFOUT2

pins to ground via a 100 pF capacitor and a 50 Ω resistor in series

on each pin.

Table 5. Bypass Switch Logic

Mode

VSW1

Undefined

High Gain Mode

Low Gain Mode

Undefined

RFIN1

RFOUT1

VCC1

RFIN2

VSW1

VSW1 VGAIN2

VPOS1

VGAIN1

100pF

λ1

λ2

C40

0.1µF

C41

1000pF

100pF

GND1 GND2 GND3

100nH

100pF

RFOUT3

C13

100pF

C14

100pF

100Ω

0Ω

100nH

1.5pF

C21

100pF

1nH

ADL5246

AMP1

AMP2

AMP3

GND

NIC PINS

TIE TO GND

VVA1

VVA2

9 12 14 17 19 22

3 10 20 23 24 25 27 29 31

0.1µF

1000pF

10pF

10nH

2.7pF

C20

0.1µF

C17

1000pF

C16

100pF

C22

100pF

100Ω

C11

100pF

100Ω

C15

100pF

RFOUT2

RFIN3

100Ω

VPOS2

100nH

C23

100pF

C26

0.1µF

C25

1000pF

C24

100pF

VCC2

λ3

Figure 74. Basic Connections

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