STRFNFCA datasheet(50/74 Pages) STMICROELECTRONICS

50 / 74 page

Electrical characteristics

STRFNFCA

50/74

Doc ID 023077 Rev 10

6.4

SPI characteristics

The STRFNFCA supports (CPOL = 0, CPHA = 0) and (CPOL = 1, CPHA = 1) modes.

Figure 12.

SPI timing diagram (Slave mode and CPOL = 0, CPHA = 0)

Table 42.

SPI interface characteristics

Symbol

Parameter

Condition

Min.

Max.

Unit

fSCK

1/ tc(SCK)

SPI clock frequency

2.0

MHz

VIL

Input low voltage

0.3

VPS

VIH

Input high voltage

0.7

VOL

Output low voltage

0.4

VOH

Output high voltage

0.7

tSU(NSS)

(1)

Values based on design simulation and/or characterization results, and not on tested in production.

NSS setup time

th(NSS)

(1)

NSS hold time

tCH(SCKL)

(1)

Clock low time

200

tCH(SCKH)

(1)

Clock high time

200

tSU(SI)

(1)

Data slave Input setup time

th(SI)

(1)

Data slave Input hold time

tv(SO)

(1)

Data slave output valid time

th(SO)

(1)

Data slave output hold time

After enable

edge

Cb_SPI_IN

Capacitive load for input pins NSS,

CLK, MOSI

3pF

Cb_SPI_OUT

Capacitive load for input pins

MOSI

MS18165V2

NSS input

tSU(NSS)

tc(SCK)

th(NSS)

tV(SO)

th(SO)

tsu(SI)

th(SI)

CPOL = 0

CPHA = 0

tCH(SCKH)

tCH(SCKL)

MSB Out

MSB In

Bit 6 Out

Bit 1 In

LSB Out

LSB In

MISO

MOSI

STRFNFCA Arkusz danych(PDF) 50 Page - STMicroelectronics

STRFNFCA Arkusz danych(HTML) 50 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74

Arkusz danych Pobierz

Link URL