XIO2001IPNP datasheet(45/141 Pages) TI1

45 / 141 page

XIO2001

www.ti.com

SCPS212I – MAY 2009 – REVISED JANUARY 2016

Product Folder Links: XIO2001

Submit Documentation Feedback

8.4.4 Command Register

The command register controls how the bridge behaves on the PCI Express interface. See Table 12 for a

complete description of the register contents.

PCI register offset:

04h

Read-only, Read/Write

Default value:

0000h

BIT NUMBER

RESET STATE

Table 12. Command Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:11

RSVD

Reserved. Returns 00000b when read.

INT_DISABLE

INTx disable. This bit enables device specific interrupts. Since the bridge does not

generate any internal interrupts, this bit is read-only 0b.

FBB_ENB

Fast back-to-back enable. The bridge does not generate fast back-to-back transactions;

therefore, this bit returns 0b when read.

SERR_ENB

SERR enable bit. When this bit is set, the bridge can signal fatal and nonfatal errors on the

PCI Express interface on behalf of SERR assertions detected on the PCI bus.

0 =

1 =

Disable the reporting of nonfatal errors and fatal errors (default)

Enable the reporting of nonfatal errors and fatal errors

STEP_ENB

Address/data stepping control. The bridge does not support address/data stepping, and

this bit is hardwired to 0b.

PERR_ENB

Controls the setting of bit 8 (DATAPAR) in the status register (offset 06h, see Status

TLP is forwarded with bad parity to conventional PCI regardless of the setting of this bit.

0 =

1 =

Disables the setting of the master data parity error bit (default)

Enables the setting of the master data parity error bit

VGA_ENB

VGA palette snoop enable. The bridge does not support VGA palette snooping; therefore,

this bit returns 0b when read.

MWI_ENB

Memory write and invalidate enable. When this bit is set, the bridge translates PCI

Express memory write requests into memory write and invalidate transactions on the PCI

interface.

0 =

1 =

Disable the promotion to memory write and invalidate (default)

Enable the promotion to memory write and invalidate

SPECIAL

Special cycle enable. The bridge does not respond to special cycle transactions; therefore,

this bit returns 0b when read.

MASTER_ENB

Bus master enable. When this bit is set, the bridge is enabled to initiate transactions on

the PCI Express interface.

0 = PCI Express interface cannot initiate transactions. The bridge must disable the

response to memory and I/O transactions on the PCI interface (default).

1 = PCI Express interface can initiate transactions. The bridge can forward memory

and I/O transactions from PCI secondary interface to the PCI Express interface.

MEMORY_ENB

Memory space enable. Setting this bit enables the bridge to respond to memory

transactions on the PCI Express interface.

0 = PCI Express receiver cannot process downstream memory transactions and must

respond with an unsupported request (default)

1 = PCI Express receiver can process downstream memory transactions. The bridge

can forward memory transactions to the PCI interface.

IO_ENB

I/O space enable. Setting this bit enables the bridge to respond to I/O transactions on the

PCI Express interface.

0 = PCI Express receiver cannot process downstream I/O transactions and must

respond with an unsupported request (default)

1 = PCI Express receiver can process downstream I/O transactions. The bridge can

forward I/O transactions to the PCI interface.

XIO2001IPNP Arkusz danych(PDF) 45 Page - Texas Instruments

XIO2001IPNP Arkusz danych(HTML) 45 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Arkusz danych Pobierz

Link URL