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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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XIO2001IPNP Arkusz danych(PDF) 12 Page - Texas Instruments |
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XIO2001IPNP Arkusz danych(HTML) 12 Page - Texas Instruments |
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12 / 141 page  12 XIO2001 SCPS212I – MAY 2009 – REVISED JANUARY 2016 www.ti.com Product Folder Links: XIO2001 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Pin Functions (continued) SIGNAL ZGU BALL NO. ZAJ BALL NO. PNP PIN NO. I/O TYPE CELL TYPE CLAMP RAIL EXTERNAL PARTS DESCRIPTION M66EN L06 M06 45 I PCI Bus PCIR Pullup resistor per PCI spec 66-MHz mode enable 0 = Secondary PCI bus and clock outputs operate at 33 MHz. If PCLK66_SEL is low then the frequency will be 25 MHz. 1 = Secondary PCI bus and clock outputs operate at 66 MHz. If PCLK66_SEL is low then the frequency will be 50 MHz. PAR F01 G01 15 I/O PCI Bus PCIR – PCI bus parity PERR G02 G03 17 I/O PCI Bus PCIR Pullup resistor per PCI spec PCI parity error PME L12 M12 67 I LV CMOS VDD_33_ COMBIO Pullup resistor per PCI spec Pullup resistor per PCI spec PCI power management event. This terminal may be used to detect PME events from a PCI device on the secondary bus. Note: The PME input buffer has hysteresis. REQ5 REQ4 REQ3 REQ2 REQ1 REQ0 A12 C09 C08 A08 A06 A04 C09 A09 C08 C07 C06 A04 102 105 108 110 116 119 I PCI Bus PCIR If unused, a weak pullup resistor per PCI spec PCI request inputs. These signals are used for arbitration on the secondary PCI bus when an external arbiter is not used. REQ0 is used as the GNT for the bridge when an external arbiter is used. PRST N07 L07 51 O PCI Bus PCIR – PCI reset. This terminal is an output to the secondary PCI bus. SERR G03 G02 16 I/O PCI Bus PCIR Pullup resistor per PCI spec PCI system error STOP G01 H01 18 I/O PCI Bus PCIR Pullup resistor per PCI spec PCI stop TRDY H01 J02 22 I/O PCI Bus PCIR Pullup resistor per PCI spec PCI target ready JTAG JTAG_TCK M12 N12 65 I LV CMOS VDD_33 Optional pullup resistor JTAG test clock input. This signal provides the clock for the internal TAP controller. Note: This terminal has an internal active pullup resistor. The pullup is active at all times. Note: This terminal should be tied to ground or pulled low if JTAG is not required. JTAG_TDI N12 L10 63 I LV CMOS VDD_33 Optional pullup resistor JTAG test data input. Serial test instructions and data are received on this terminal. Note: This terminal has an internal active pullup resistor. The pullup is active at all times. Note: This terminal can be left unconnected if JTAG is not required. JTAG_TDO M11 N11 61 O LV CMOS VDD_33 – JTAG test data output. This terminal the serial output for test instructions and data. Note: This terminal can be left unconnected if JTAG is not required. JTAG_TMS L10 L11 64 I LV CMOS VDD_33 Optional pullup resistor JTAG test mode select. The signal received at JTAG_TMS is decoded by the internal TAP controller to control test operations. Note: This terminal has an internal active pullup resistor. The pullup is active at all times. Note: This terminal can be left unconnected if JTAG is not required. |
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