XIO2001IPNP datasheet(89/141 Pages) TI1

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XIO2001

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SCPS212I – MAY 2009 – REVISED JANUARY 2016

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Table 59. Pre-Fetch Agent Request Limits Register Description (continued)

BIT

FIELD NAME

ACCESS

DESCRIPTION

7:6

PFA_CPL_CACHE_

MODE

Completion cache mode. Determines the rules for completing the caching process.

00 = No caching.

•

Pre-fetching is disabled.

•

All remaining read completion data will be discarded after any of the

data has been returned to the PCI master.

01 = Light caching.

•

Pre-fetching is enabled.

•

All remaining read completion data will be discarded after data has

been returned to the PCI master and the PCI master terminated the

transfer.

•

All remaining read completion data will be cached after data has

been returned to the PCI master and the bridge has terminated the

transfer with RETRY.

10 = Full caching.

•

Pre-fetching is enabled.

•

All remaining read completion data will be cached after data has

been returned to the PCI master and the PCI master terminated the

transfer.

•

All remaining read completion data will be cached after data has

been returned to the PCI master and the bridge has terminated the

transfer with RETRY.

11 = Reserved.

5:4

RSVD

Reserved. Returns 00b when read.

3:0

PFA_REQ_LENGT

H_LIMIT

Request Length Limit. Determines the number of bytes in the thread that the pre-fetch

agent will read for that thread.

0000 = 64 bytes

0001 = 128 bytes

0010 = 256 bytes

0011 = 512 bytes

0100 = 1 Kbytes

0101 = 2 Kbytes

0110 = 4 Kbytes

0111 = 8 Kbytes

1000:1111 = Reserved

8.4.77 Cache Timer Transfer Limit Register

This register is used to set the number of PCI cycle starts that have to occur without a read hit on the completion

data buffer, before the cache data can be discarded. See Table 60 for a complete description of the register

contents.

PCI register offset:

EAh

Read/Clear

Default value:

0008h

BIT NUMBER

RESET STATE

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