AD6676EBZ datasheet(36/90 Pages) AD

36 / 90 page

AD6676

Data Sheet

Rev. A | Page 36 of 90

R and N Dividers

The phase/frequency detector (PFD) requires a 10 MHz to 80 MHz

clock. When fCLK = 200 MHz, the R divider must be set to divide by

4 so that fPFD = fCLK/RDIV = 50 MHz, which is within the supported

range. Table 11 shows the mapping from RDIV to the value of

Table 11. R Divider Settings for Register 0x2BB

RDIV

0b00

0b01

0b10

0.5

0b11

Note that operating with the highest permissible fPFD minimizes

the clock synthesizer reference spur because the PLL filter

bandwidth is fixed at 200 kHz. For a sinusoidal clock input

signal that has a limited input slew rate, operation with an input

frequency that is 2× or 4× the desired fPFD can also result in a

slight improvement in phase noise performance.

Because the ADC clock is obtained by dividing the VCO clock

by 2, the N-divider must be set according to

N = 2FADC/fPFD =2 × 3.2 GHz/50 MHz =128 = 0x80

The value of N is programmed by writing the LSB (0x80) to

in Step 1 of Table 27.

Charge Pump Current and Calibration

The charge pump current setting (Register 0x2AC) is given by

))

(min(

round







ADC

PFD

(6)

For the FADC and fPFD values used in this example, ICP evaluates

to 25, or 0x19; this value is programmed in Step 4 of Table 27.

The charge pump also must be calibrated during the clock

synthesizer initialization phase. Calibration is triggered via

is inversely proportional to the PFD frequency. For example,

using fPFD = 10 MHz requires a maximum 4 ms wait period but

increasing fPFD to 80 MHz decreases the maximum wait period

by a factor of 8 to 0.5 ms. Alternatively, poll Bit 0 of Register 0x2BC;

charge pump calibration is complete when this bit is set.

VCO Configuration and Calibration

VCO configuration consists of writing to the SPI registers in

Table 12 that control the VCO core bias, temperature compensation,

and varactor settings. These settings depend on the VCO

frequency and are optimized via characterization to ensure

proper operation of the PLL over supply and temperature.

Table 12. VCO Configuration Settings vs. FADC

FADC (MHz)

2940 to 2950

0x37

0xF0

2950 to 3100

0x37

0xE0

3100 to 3200

0x37

0xD0

The VCO also must be calibrated during the clock synthesizer

initialization phase to ensure proper operation over its full

temperature range. VCO calibration is triggered via

the calibration again being inversely proportional to the PFD

frequency. Specifically, fPFD = 10 MHz requires a 2 ms wait

period whereas fPFD = 80 MHz decreases the wait period by a

factor of 8 to 0.25 ms. Alternatively, poll Bit 1 of Register 0x2BC;

VCO calibration is complete when this bit is clear.

After the initialization process is complete, verify that Bit 3 of

AD6676EBZ Arkusz danych(PDF) 36 Page - Analog Devices

AD6676EBZ Arkusz danych(HTML) 36 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

Arkusz danych Pobierz

Link URL