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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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AD6676EBZ Arkusz danych(PDF) 88 Page - Analog Devices |
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AD6676EBZ Arkusz danych(HTML) 88 Page - Analog Devices |
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88 / 90 page  AD6676 Data Sheet Rev. A | Page 88 of 90 CLKSYN Charge Pump Calibration Register Address: 0x2AD, Reset: 0x00, Name: EN_CP_CAL Table 126. Bit Descriptions for EN_CP_CAL Bits Bit Name Description Reset Access [7:6] EN_CP_CAL 0x0 RW [6:0] RESERVED 0x0 RW CLKSYN VCO Varactor Register Address: 0x2B7, Reset: 0xD0, Name: CLKSYN_VCO_VAR Table 127. Bit Descriptions for CLKSYN_VCO_VAR Bits Bit Name Description Reset Access [7:4] VCO_VAR VCO Varactor Setting. 0xD0 RW [3:0] RESERVED CLKSYN Reference Divider and SYSREF Control Register Address: 0x2BB, Reset: 0xB9, Name: CLKSYN_R_DIV Table 128. Bit Descriptions for CLKSYN_R_DIV Bits Bit Name Description Reset Access [7:6] R_DIV 00 = div-by-1; 01 = div-by-2; 10 = div-by-4; 11 = multiply-by-2. 10 RW [5:4] RESERVED 0x3 RW 3 SYSREF_CTRL SYSREF Input Sampling Clock. 1 RW 0 = use clock synthesizer reference clock. 1 = use internal clock at F ADC/2 (use for nonclock synthesizer case). 2 CLKIN_IMPED CLKIN Impedance. 0 RW 0 = configure CLK± as 100 Ω termination, configuration for clock synthesizer disabled. 1 = configure CLK+ as high-Z, configuration for clock synthesizer enabled. [1:0] RESERVED 0x1 RW CLKSYN Status Register Address: 0x2BC, Reset: 0x80, Name: CLKSYN_STATUS Table 129. Bit Descriptions for CLKSYN_STATUS Bits Bit Name Description Reset Access [7:4] RESERVED 0x8 R 3 PLL_LCK Clock Synthesizer Lock Bit (1 = lock). 0x0 R 2 RESERVED 0x0 R 1 VCO CAL BUSY VCO Calibration Busy (0 = done). 0x0 R 0 CP CAL DONE Charge Pump Calibration Done (1 = done). 0x0 R |
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