CLC5506PCASM datasheet(8/12 Pages) NSC

8 / 12 page

APPLICATION NOTE

Description

Figure 1 above shows the CLC5506 functional block dia-

gram overview.

The LNA (Low Noise Amplifier) is responsible for maintaining

a nominal input impedance of 200

Ω with minimum noise

contribution and some finite and fixed amount of gain (

∼4).

Exceptional Noise Figure (NF) performance of 4.8dB (@

Gain = 25.75dB) is achieved by utilizing an active impedance

matching circuit technique which overcomes the inevitable

3dB NF penalty when using passive shunt matching.

The LNA stage is immediately followed by a transconduc-

tance stage (Gm) which then converts the LNA’s voltage out-

put into a differential current output with fixed gain.

The 6-bit D/A converter, which processes the digital code

read into the device using the MICROWIRE interface, con-

sists of a 6-bit R2R ladder. In order to achieve true

″Linear in

″ gain control at the output, the D/A converter output is

processed by a

″Linear to Exponential″ converter block be-

fore being used to set the gain of the input signal. The

″Lin-

ear to Exponential

″ block and the ″Temperature Compensa-

tion

″ blocks work in conjunction to achieve gain stability over

the temperature range. Finally, the output stage consists of a

variable gain cell with open Collector output. This variable

gain cell sets the signal channel gain in accordance with the

value of the digital code.

Gain Control

The CLC5506 minimum gain is at 10dB nominal. There are

a total of 64 distinct gain control codes possible (serial data

input through Data In pin) at 0.25dB/code resulting in a maxi-

mum nominal gain of 25.75dB.

Therefore, the overall gain can be written as:

Gain (dB) = 10dB + N

code * 0.25 (dB/code)

where N

code refers to the decimal equivalent of the 6-bit gain

control code.

TABLE 1.

Gain

Typical Gain Setting (dB)

Note

Minimum Gain Setting

10.25

10.5

***

10 + 0.25

***

25.50

25.75

Maximum Gain Setting

Power Down

The CLC5506 is able to go to a Power Down mode in order

to minimize its power consumption to a fraction of its nominal

value. The Power Down mode is activated through the MI-

CROWIRE interface by clocking in a

″1″ into the Power

Down shift register prior to allowing LE (pin 5) to go high. Re-

fer to

Figure 2 and Figure 3 for more information.

In Power Down mode, the CLC5506 sinks less than 35µA.

The CLC5506 will wake up to the requested gain level speci-

fied by Data In through the MICROWIRE interface.

When V

CC is first applied, the device is configured such that

it would always

″wake up″ with a nominal gain of 17.75dB

code = 3).

DS101050-17

FIGURE 1. CLC5506 Functional Block Diagram

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