TAS3208IPZP datasheet(50/79 Pages) TI1

50 / 79 page

SCL

HD;DAT

SU;DAT

LOW

HD;STA

BUF

HIGH

SU;STA

SU;STO

SDA

TAS3208

SLES201E

– JANUARY 2007 – REVISED MARCH 2011

www.ti.com

PARAMETER MEASUREMENT INFORMATION (continued)

Figure 38. I2C SCL and SDA Timing

Master I

2C Load RAM Block Formats

This section describes the format of the data that is stored in an external memory device and downloaded to the

TAS3208 via the master I2C bus.

Master I2C Memory Block Header

Table 11. 1 Memory Block Header

STARTING

DATA BLOCK FORMAT

SIZE

NOTES

BYTE

Checksum MSB

2 bytes

Checksum of byte 2 through N + 12

Checksum LSB

Header ID byte 1 = 0x00

2 bytes

Must be 0x001F

Header ID byte 2 = 0x1F

0x00: Microprogram RAM or termination header

0x01: Micro external data RAM

0x02: DSP program RAM

Memory to be loaded

1 byte

0x03 : DSP coefficient RAM

0x04: DSP data RAM

0x05

–0x0F: Reserved

0x00

1 byte

Unused

Start memory address MSB

2 bytes

If this is a termination header, this value is 0000.

Start memory address LSB

Total number of byte transferred MSB

Header size (12) + data byte + last checksum byte. If this is

2 bytes

a termination header, this value is 0000.

Total number of byte transferred LSB

0x00

1 byte

Unused

0x00

1 byte

Unused

Submit Documentation Feedback

Product Folder Link(s): TAS3208

TAS3208IPZP Arkusz danych(PDF) 50 Page - Texas Instruments

TAS3208IPZP Arkusz danych(HTML) 50 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

Arkusz danych Pobierz

Link URL