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TAS3208IPZP Arkusz danych(PDF) 11 Page - Texas Instruments

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Numer części TAS3208IPZP
Szczegółowy opis  DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE
PDF  79 Pages
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Producent  TI1 [Texas Instruments]
Strona internetowa  http://www.ti.com
Logo TI1 - Texas Instruments

TAS3208IPZP Arkusz danych(HTML) 11 Page - Texas Instruments

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LRCLK
SCLK
2-Channel Left-Justified Stereo Input
Left Channel
Right Channel
LSB
MSB
MSB
LSB
32 clks
32 clks
24-Bit Mode
20-Bit Mode
16-Bit Mode
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LRCLK
SCLK
2-Channel Right-Justified (Sony Format) Stereo Input
Left Channel
Right Channel
LSB
MSB
MSB
LSB
32 clks
32 clks
24-Bit Mode
20-Bit Mode
16-Bit Mode
23 22 21 20 19 18 17 16 15 14 13
10
9
8
7
6
5
4
3
2
1
0
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19 18 17 16 15 14 13
10
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0
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15 14 13
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23 22 21 20 19 18 17 16 15 14 13
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9
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1
0
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19 18 17 16 15 14 13
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TAS3208
www.ti.com
SLES201E
– JANUARY 2007 – REVISED MARCH 2011
Discrete Left-Justified (LJ) Timing
Left-justified timing uses an LRCLK to define when the data being transmitted is for the left channel or right
channel. The LRCLK is HIGH for the left channel and LOW for the right channel. A bit clock running at 64
× Fs is
used to clock in the data. The first bit of data appears on the data lines at the same time the LRCLK toggles. The
data is written MSB first and is valid on the rising edge of bit clock. The TAS3208 will mask unused trailing data
bit positions.
A.
All data are presented in 2
's complement form with MSB first.
Figure 6. SAP Left-Justified 64
× Fs Format
Discrete Right-Justified (RJ) Timing
Right-justified timing uses an LRCLK to define when the data being transmitted is for the left channel or right
channel. The LRCLK is HIGH for the left channel and LOW for the right channel. A bit clock running at 64
× Fs is
used to clock in the data. The first bit of data appears on the data 8-bit clock periods (for 24-bit data) after
L/RCLK toggles. In RJ mode, the LSB of data is always clocked by the last bit clock before L/RCLK transitions.
The data is written MSB first and is valid on the rising edge of bit clock. The TAS3208 will mask unused leading
data bit positions.
A.
All data are presented in 2s-complement form with MSB first.
Figure 7. SAP Right-Justified 64
× Fs Format
Copyright
© 2007–2011, Texas Instruments Incorporated
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