CS8406

26

DS580F1

SIJUST - Justification of SDIN data relative to ILRCK

Default = ‘0’

0 - Left-justified

1 - Right-justified

SIDEL - Delay of SDIN data relative to ILRCK, for left-justified data formats

Default = ‘0’

0 - MSB of SDIN data occurs in the first ISCLK period after the ILRCK edge (left justified mode)

1 - MSB of SDIN data occurs in the second ISCLK period after the ILRCK edge (I²S mode)

SISPOL - ISCLK clock polarity

Default = ‘0’

0 - SDIN sampled on rising edges of ISCLK

1 - SDIN sampled on falling edges of ISCLK

SILRPOL - ILRCK clock polarity

Default = ‘0’

0 - SDIN data is for the left channel when ILRCK is high

1 - SDIN data is for the right channel when ILRCK is high

8.6

Interrupt 1 Status (07h) (Read Only)

For all bits in this register, a ‘1’ means the associated interrupt condition has occurred at least once since the register

was last read. A ‘0’ means the associated interrupt condition has NOT occurred since the last reading of the register.

Reading the register resets all bits to ‘0’, unless the interrupt mode is set to level and the interrupt source is still true.

Status bits that are masked off in the associated mask register will always be ‘0’ in this register. This register defaults

to 00h.

TSLIP - AES3 transmitter source data slip interrupt

In data flows where OMCK, which clocks the AES3 transmitter, is asynchronous to the data source,

this bit will go high every time a data sample is dropped or repeated. When TCBL is an input, this bit

will go high on receipt of a new TCBL signal.

EFTC - E to F C-buffer transfer interrupt.

The source for this bit is true during the E to F buffer transfer in the C bit buffer management process.

7

6

5

43210

TSLIP

0

0

000

EFTC

0