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DS3134

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Signal Name:

JTMS

Signal Description:

JTAG IEEE 1149.1 Test Mode Select

Signal Type:

Input (with internal 10k pull up)

This signal is sampled on the rising edge of JTCLK and is used to place the test port into the various

defined IEEE 1149.1 states. If not used, this signal should be pulled high. This signal has an internal pull-

up.

2.5 PCI BUS SIGNAL DESCRIPTION

Signal Name:

PCLK

Signal Description:

PCI & System Clock

Signal Type:

Input (Schmitt triggered)

This clock input is used to provide timing for the PCI bus and to the internal logic of the device. A 25

MHz to 33 MHz clock with a nominal 50% duty cycle should be applied here.

Signal Name:

PRST*

Signal Description:

PCI Reset

Signal Type:

Input

This active low input is used to force an asynchronous reset to both the PCI bus and the internal logic of

the device. When forced low, this input forced all the internal logic of the device into its default state and

it forces the PCI outputs into tri-state and the TD[15:0] output port data signals high.

Signal Name:

PAD0 to PAD31

Signal Description:

PCI Address & Data Multiplexed Bus

Signal Type:

Input / Output (tri-state capable)

Both Address and Data information are multiplexed onto these signals. Each bus transaction consists of

an address phase followed by one or more data phases. Data can be either read or written in bursts.

During the first clock cycle of a bus transaction, the address is transferred. When the Little-Endian format

is selected, PAD[31:24] is the msb of the DWORD, when Big-Endian is selected, PAD[7:0] contain the

msb. When the device is an initiator, these signals are always outputs during the address phase. They

remain outputs for the data phase(s) in a write transaction and become inputs for a read transaction.

When the device is a target, these signals are always inputs during the address phase. They remain inputs

for the data phase(s) in a read transaction and become outputs for a write transaction. When the device is

not involved in a bus transaction, these signals remain tri-stated. These signals are always updated and

sampled on the rising edge of PCLK.

Signal Name:

PCBE0* / PCBE1* / PCBE2* / PCBE3*

Signal Description:

PCI Bus Command and Byte Enable

Signal Type:

Input / Output (tri-state capable)

Bus Command and Byte Enables are multiplexed onto the same PCI signals. During an address phase,

these signals define the Bus Command. During the data phase, these signals as used as Bus Enables.

During data phases, PCBE0 refers to the PAD[7:0] and PCBE3 refers to PAD[31:24]. When this signal is

high, the associated byte is invalid, when low; the associated byte is valid. When the device is an

initiator, this signal is an output and is updated on the rising edge of PCLK. When the device is a target,

this signal is input and is sampled on the rising edge of PCLK. When the device is not involved in a bus

transaction, these signals are tri-stated.

Signal Name:

PPAR

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