AP0100CS datasheet(38/73 Pages) ONSEMI

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AP0100CS HDR: Image Signal Processor (ISP)

Overlay Capability

AP0100CS/D Rev. 6, Pub. 1/16 EN

©Semiconductor Components Industries, LLC,2016.

Figure 26:

Zoom and Look Right

Overlay Capability

Figure 27 highlights the graphical overlay data flow of the AP0100CS. The images are

separated to fit into 4KB blocks of memory after compression.

• Up to seven overlays may be blended simultaneously

• Overlay size up to 720 x 576 pixels rendered

• Selectable readout: rotating order is user programmable

• Dynamic movement through predefined overlay images

• Palette of 32 colors out of 16 million with 16 colors per bitmap

• Each color has a YCbCr (8-8-8 bit) and 8 bits for the Alpha value (Transparency).

• Each layer has a built in fader which when enabled scales the Alpha value for each

pixel.

• Blend factors may be changed dynamically to achieve smooth transitions

The overlay engine is controlled through host commands that allow a bitmap to be

written piecemeal to a memory buffer through the two-wire serial interface, and

through a DMA chanel direct from SPI Flash memory. Multiple encoding passes may be

required to fit an image into a 4KB block of memory; alternatively, the image can be

divided into two or more blocks to make the image fit. Every graphic image may be posi-

tioned in an x/y direction and overlap with other graphic images.

The host may load an image at any time. Under control of DMA assist, data are trans-

ferred to the off-screen buffer in compressed form. This assures that no display data are

corrupted during the replenishment of the seven active overlay buffers.

AP0100CS Arkusz danych(PDF) 38 Page - ON Semiconductor