M24SR16-Y datasheet(71/89 Pages) STMICROELECTRONICS

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M24SR16-Y

I2C DC and AC parameters

Table 79. I2C AC characteristics (1 MHz)

Test conditions specified in Table 74

(preliminary data based on design simulations)

Symbol

Alt.

Parameter

Min.

Max.

Unit

fSCL

Clock frequency

0.05

1000

kHz

tCHCL (1)

1. tCHCL timeout.

tHIGH Clock pulse width high

260

tCLCH (2)

2. tCLCH timeout.

tLOW

Clock pulse width low

500

tXH1XH2

Input signal rise time

(3)

3. There is no min. or max. value for the input signal rise and fall times. It is however recommended by the I²C

specification that the input signal rise and fall times be less than 120 ns when fC < 1 MHz.

(3)

tXL1XL2

Input signal fall time

(3)

tDL1DL2

SDA (out) fall time

120

tDXCX

tSU:DAT Data in set up time

tCLDX

tHD:DAT Data in hold time

tCLQX

tDH

Data out hold time

100

tCLQV (4)(5)

4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or

rising edge of SDA.

5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8VCC in a

compatible way with the I2C specification (which specifies tSU:DAT (min) = 100 ns), assuming that the Rbus

× Cbus time constant is less than 500 ns (as specified in Figure 17).

tAA

Clock low to next data valid (access time)

450

tCHDX (6)

6. For a reStart condition, or following a write cycle.

tSU:STA Start condition set up time

250

tDLCL

tHD:STA Start condition hold time

250

tCHDH

tSU:STO Stop condition set up time

250

tDHDL

tBUF

Time between Stop condition and next Start

condition

500

tWR

I²C write time in one page

I²C write time up to 246 bytes

150

tNS (7)

7. Characterized only, not tested in production.

Pulse width ignored (input filter on SCL and

SDA)

-80

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