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ST7LITE49K2 Arkusz danych(PDF) 43 Page - STMicroelectronics |
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ST7LITE49K2 Arkusz danych(HTML) 43 Page - STMicroelectronics |
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43 / 245 page  ST7LITE49K2 Supply, reset and clock management 43/245 7.3 Reset sequence manager (RSM) 7.3.1 Introduction The reset sequence manager includes three RESET sources as shown in Figure 15: ● External RESET source pulse ● Internal LVD RESET (Low Voltage Detection) ● Internal WATCHDOG RESET Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code. Refer to Section 12.2.1 on page 189 for further details. These sources act on the RESET pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory mapping. The basic RESET sequence consists of 3 phases as shown in Figure 14: ● Active Phase depending on the RESET source ● 256 CPU clock cycle delay (see Table 7) Table 6. ST7 clock sources Hardware configuration OSC1 OSC2 EXTERNAL ST7 SOURCE OSC1 OSC2 LOAD CAPACITORS ST7 CL2 CL1 OSC1 OSC2 ST7 |
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