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ST7LITE49K2 Arkusz danych(PDF) 46 Page - STMicroelectronics |
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ST7LITE49K2 Arkusz danych(HTML) 46 Page - STMicroelectronics |
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46 / 245 page  Supply, reset and clock management ST7LITE49K2 46/245 7.3.5 Internal watchdog reset The Reset sequence generated by an internal watchdog counter overflow is shown in Figure 16: Reset sequences Starting from the watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least tw(RSTL)out. Figure 16. Reset sequences tw(RSTL)out RUN RUN WATCHDOG RESET INTERNAL RESET (256 or 4096 TCPU) VECTOR FETCH ACTIVE PHASE VDD RUN RESET PIN EXTERNAL WATCHDOG ACTIVE PHASE VIT+(LVD) VIT-(LVD) th(RSTL)in RUN WATCHDOG UNDERFLOW RESET RESET SOURCE EXTERNAL RESET LVD RESET ACTIVE PHASE |
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