T48C862-R4 datasheet(7/107 Pages) ATMEL

7 / 107 page

T48C862-R4 [Preliminary]

4551C–4BMCU–01/04

Figure 4. Tolerances of Frequency Modulation

Using C

4 =9.2 pF ±2%, C5 = 6.8 pF ±5%, a switch port with CSwitch = 3 pF ±10%, stray

capacitances on each side of the crystal of C

Stray1 =CStray2 = 1 pF ±10%, a parallel

capacitance of the crystal of C

0 = 3.2 pF ±10% and a crystal with CM = 13 fF ±10%, an

FSK deviation of ±21 kHz typical with worst case tolerances of ±16.3 kHz to ±28.8 kHz

results.

CLK Output

An output CLK signal is provided for a connected microcontroller. The delivered signal is

CMOS compatible if the load capacitance is lower than 10 pF.

Clock Pulse Take Over

The clock of the crystal oscillator can be used for clocking the microcontroller. the micro-

controller block has the special feature of starting with an integrated RC-oscillator to

switch on the PLL transmitter block with ENABLE = H, and after 1 ms to assume the

clock signal of the transmission IC, so the message can be sent with crystal accuracy.

Output Matching and Power

Setting

The output power is set by the load impedance of the antenna. The maximum output

power is achieved with a load impedance of Z

Load,opt = (166 + j223) Ω. There must be a

low resistive path to V

S to deliver the DC current.

The delivered current pulse of the power amplifier is 9 mA and the maximum output

power is delivered to a resistive load of 465

Ω if the 1.0 pF output capacitance of the

power amplifier is compensated by the load impedance.

An optimum load impedance of:

Load = 465 Ω || j/(2 ×π 1.0 pF) = (166 + j223) Ω thus results for the maximum output

power of 7.5 dBm.

The load impedance is defined as the impedance seen from the PLL transmitter block’s

ANT1, ANT2 into the matching network. Do not confuse this large signal load imped-

ance with a small signal input impedance delivered as input characteristic of RF

amplifiers and measured from the application into the IC instead of from the IC into the

application for a power amplifier.

Less output power is achieved by lowering the real parallel part of 465

Ω where the

parallel imaginary part should be kept constant.

Output power measurement can be done with the circuit shown in Figure 5 on page 8.

Note that the component values must be changed to compensate the individual board

pa r a s i t i c s u n ti l th e PL L tr an s m i tte r bl oc k h a s the r i gh t l o a d im pe da nc e

Load,opt = (166 + j223) Ω. Also the damping of the cable used to measure the output

power must be calibrated.

XTAL

Stray1

Stray2

Crystal equivalent circuit

Switch

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