HT82K95AE datasheet(16/43 Pages) HOLTEK

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HT82K95EE/HT82K95AE

Rev. 1.50

April 13, 2012

1. In the pulse width measurement mode, the

T0ON/T1ON will be cleared automatically after the mea-

surement cycle is completed. But in the other two

modes the T0ON/T1ON can only be reset by instruc-

tions. The overflow of the Timer/Event Counter 0/1 is

one of the wake-up sources. No matter what the opera-

tion mode is, writinga0to ET0I/ET1I can disable the

corresponding interrupt services.

In the case of Timer/Event Counter 0/1 OFF condition,

writing data to the Timer/Event Counter 0/1 preload regis-

ter will also reload that data to the Timer/Event Counter

0/1. But if the Timer/Event Counter 0/1 is turned on, data

written to it will only be kept in the Timer/Event Counter

0/1 preload register. The Timer/Event Counter 0/1 will still

operate until overflow occurs (a Timer/Event Counter 0/1

reloading will occur at the same time). When the

Timer/Event Counter 0/1 (reading TMR0/TMR1) is read,

the clock will be blocked to avoid errors. As clock blocking

may results in a counting error, this must be taken into

consideration by the programmer.

Input/Output Ports

There are 32 bidirectional input/output lines in the

microcontroller, labeled from PA to PD, which are

mapped to the data memory of [12H], [14H], [16H] and

[18H] respectively. All of these I/O ports can be used for

input and output operations. For input operation, these

ports are non-latching, that is, the inputs must be ready

at the T2 rising edge of instruction

²MOV A,[m]² (m=12H,

14H, 16H or 18H). For output operation, all the data is

latched and remains unchanged until the output latch is

rewritten.

Each I/O line has its own control register (PAC, PBC,

PCC, PDC) to control the input/output configuration.

With this control register, CMOS/NMOS/PMOS output

or Schmitt trigger input with or without pull-high resistor

structures can be reconfigured dynamically under soft-

ware control. To function as an input, the corresponding

latch of the control register must write a

²1². The input

source also depends on the control register. If the con-

trol register bit is

²1², the input will read the pad state. If

the control register bit is

²0², the contents of the latches

will move to the internal bus. The latter is possible in the

²read-modify-write² instruction. For output function,

CMOS/NMOS/PMOS configurations can be selected

(NMOS and PMOS are available for PA only). These

control registers are mapped to locations 13H, 15H, 17H

and 19H.

After a chip reset, these input/output lines remain at high

levels or floating state (depending on the pull-high op-

tions). Each bit of these input/output latches can be set

or cleared by

²SET [m].i² and ²CLR [m].i² (m=12H, 14H,

16H or 18H) instructions.

Some instructions first input data and then follow the

output operations. For example,

²SET [m].i², ²CLR

[m].i

², ²CPL [m]², ²CPLA [m]² read the entire port states

into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or the accumulator.

Each line of all the I/O ports have the capability of wak-

ing up the device.

There are pull-high (PA only) options available for I/O

lines. Once the pull-high option of an I/O line is selected,

the I/O line have pull-high resistor. Otherwise, the

pull-high resistor is absent. It should be noted that a

non-pull-high I/O line operating in input mode will cause

a floating state.

It is recommended that unused or not bonded out I/O

lines should be set as output pins by software instruction

to avoid consuming power under input floating state.

V D D

P A 0 ~ P A 6 , P A 7 / T M R

P B 0 ~ P B 7

P C 0 ~ P C 7

P D 0 ~ P D 7

R e a d D a t a R e g i s t e r

C o n t r o l B i t

P H

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

D a t a B i t

P L

W a k e - u p f o r a n y I / O P o r t

P A 7 / T M R

P A O u t p u t

C o n f i g u r a t i o n

W a k e - u p O p t i o n f o r a n y I / O P o r t

C K

Input/Output Ports

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