HT82K95AE datasheet(18/43 Pages) HOLTEK

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HT82K95EE/HT82K95AE

Rev. 1.50

April 13, 2012

· Acknowledge

All addresses and data words are serially transmitted

to and from the EEPROM in 8-bit words. The

EEPROM sends a zero to acknowledge that it has re-

ceived each word. This happens during the ninth clock

cycle.

Device Addressing

The 1K EEPROM devices all require an 8-bit device ad-

dress word following a start condition to enable the chip

for a read or write operation. The device address word

consist of a mandatory one, zero sequence for the first

four most significant bits (refer to the diagram showing

the Device Address). This is common to all the

EEPROM device.

The next three bits are the fixed to be

²0².

The 8th bit of device address is the read/write operation

select bit. A read operation is initiated if this bit is high

and a write operation is initiated if this bit is low.

If the comparison of the device address succeed the

EEPROM will output a zero at ACK bit. If not, the chip will

return to a standby state.

Write Operations

· Byte write

A write operation requires an 8-bit data word address

following the device address word and acknowledg-

ment. Upon receipt of this address, the EEPROM will

again respond with a zero and then clock in the first

8-bit data word. After receiving the 8-bit data word, the

EEPROM will output a zero and the addressing de-

vice, such as a microcontroller, must terminate the

write sequence with a stop condition. At this time the

EEPROM enters an internally-timed write cycle to the

non-volatile memory. All inputs are disabled during

this write cycle and EEPROM will not respond until the

write is completed (refer to Byte write timing).

· Acknowledge polling

To maximise bus throughput, one technique is to allow

the master to poll for an acknowledge signal after the

start condition and the control byte for a write com-

mand have been sent. If the device is still busy imple-

menting its write cycle, then no ACK will be returned.

The master can send the next read/write command

when the ACK signal has finally been received.

· Read operations

The data EEPROM supports three read operations,

namely, current address read, random address read

and sequential read. During read operation execution,

the read/write select bit should be set to

²1².

· Current address read

The internal data word address counter maintains the

last address accessed during the last read or write op-

eration, incremented by one. This address stays valid

S C L

S D A

D a t a a l l o w e d

t o c h a n g e

A d d r e s s o r

a c k n o w l e d g e

v a l i d

S t o p

c o n d i t i o n

S t a r t

c o n d i t i o n

N o A C K

s t a t e

R / W

D e v i c e A d d r e s s

R / W

D e v i c e a d d r e s s

W o r d a d d r e s s

D A T A

A C K

S t o p

S t a r t

S D A

A C K

Byte Write Timing

S e n d W r i t e C o m m a n d

S e n d S t o p C o n d i t i o n

t o I n i t i a t e W r i t e C y c l e

S e n d S t a r t

S e n d C o t r o l l B y t e

w i t h R / W = 0

( A C K = 0 ) ?

N e x t O p e r a t i o n

N o

Y e s

Acknowledge Polling Flow

D e v i c e a d d r e s s

D A T A

A C K

S t o p

S t a r t

S D A

N o A C K

Current Read Timing

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