ECT25S32 datasheet(20/44 Pages) E-CMOS

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5B10N-Rev.F001

ECT25S32

32M BIT SPI NOR FLASH

Quad Output Fast Read (6BH)

See Figure 13, the Quad Output Fast Read instruction is followed by 3-byte address (A23-A0)

and a dummy byte, each bit being latched in during the rising edge of SCLK, then the memory

contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1 and IO0. The first byte

addressed can be at any location. The address is automatically incremented to the next higher

address after each byte of data is shifted out.

Figure 13. Quad Output Fast Read Sequence Diagram

Dual I/O Fast Read (BBH)

See Figure 14, the Dual I/O Fast Read instruction is similar to the Dual Output Fast Read

instruction but with the capability to input the 3-byte address (A23-

0) and a “Continuous Read

Mode”byte 2-bit per clock by SI and SO, each bit being latched in during the rising edge of

SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The first

byte addressed can be at any location. The address is automatically incremented to the next

higher address after each byte of data is shifted out.

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