ECT25S32 datasheet(29/44 Pages) E-CMOS

29 / 44 page

E-CMOS Corp. (www.ecmos.com.tw)

Page 29 of 44

5B10N-Rev.F001

ECT25S32

32M BIT SPI NOR FLASH

Figure 24. Read Security Registers instruction Sequence Diagram

Erase Security Registers (44H)

The ECT25S32 provides three 256-byte Security Registers which can be erased and

programmed individually. These registers may be used by the system manufacturers to store

security and other important information separately from the main memory array.

See Figure 25, the Erase Security Registers instruction is similar to Sector/Block Erase

instruction.A Write Enable instruction must previously have been executed to set the Write

Enable Latch bit. The Erase Security Registers instruction sequence: /CS goes low sending

Erase Security Registers instruction /CS goes high. /CS must be driven high after the eighth bit

of the instructioncode has been latched in otherwise the Erase Security Registers instruction is

not executed. Assoon as /CS is driven high, the self-timed Erase Security Registers cycle

(whose duration is tSE) isinitiated. While the Erase Security Registers cycle is in progress, the

Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In

Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is

completed. At some unspecified time before the cycle is completed, the Write Enable Latch

bit is reset. The Security Registers Lock Bit (LB) in the Status Register can be used to OTP

protect the security registers. Once the LB bit is set to 1, the Security Registers will be

permanently locked; the Erase Security Registers instruction will be ignored.

Address

A23-A16

A15-A8

A7-A0

Security Registers 1

00H

01H

Don

’t Care

Security Registers 2

00H

02H

Don

’t Care

Security Registers 3

00H

03H

Don

’t Care

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