ECT25S32 datasheet(22/44 Pages) E-CMOS

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5B10N-Rev.F001

ECT25S32

32M BIT SPI NOR FLASH

Quad I/O Fast Read (EBH)

See Figure 16, the Quad I/O Fast Read instruction is similar to the Dual I/O Fast Read

Instruction but with the capability to input the 3-byte address (A23-0) and a

“Continuous

Read Mode” byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO3, IO4, each bit being

latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit per

clock cycle from IO0, IO1, IO2, IO3. The first byte addressed can be at any location. The

address is automatically incremented to the next higher address after each byte of data is

shifted out. The Quad Enable bit (QE) of Status Register must be set to enable for the Quad

I/O Fast read instruction.

Figure 16. Quad I/O Fast Read Sequence Diagram (M7-0= 0XH or not AXH)

Quad I/O Fast R

ead with “Continuous Read Mode”

See Figure17, the Quad I/O Fast Read instruction can further reduce instruction overhead

through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-

A0). If the

“Continuous Read Mode” bits (M7-0) =AXH, then the next Quad I/O

Fast Read instruction (after /CS is raised and then lowered) does not require the EBH

instruction code. If the“

Continuous Read Mode” bits (M7-0) are any value other than AXH,

the next instruction requires the first EBH instruction code, thus returning to normal operation.

A “Continuous Read Mode” Reset instruction can be used to reset (M7-0) before issuing

normal instruction.

Figure 17. Quad I/O Fast Read Sequence Diagram (M7-0= AXH)

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