AD6652BBC datasheet(52/76 Pages) AD

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AD6652

Rev. 0 | Page 52 of 76

PCLKn

tDPREQ

PxREQ

PxACK

tDPP

Px[15:0]

I[15:0]

Q[15:0]

PxIQ

PxCH[1:0]

PxCH[0] = AGC #

PxCH[1] = 0

RSSI[11:0]

PxCH[0] = AGC #

PxCH[1] = 1

tDPIQ

tDPCH

Figure 58. AGC with RSSI Word

AVE PCLK MODES

e paralle

slave mode. The

de is set

s 0x1E).

he paralle

rts power up in slave mode to avoid possible

ntentions n the PCLK pin.

n master m de, PCLK is an output whose frequency is the

lo k frequency divided by the PCLK divisor. Because

lues for PCLK_divisor[2:1] can range from 0 to 3, integer

ors of

2, 4,or 8, respectively, can be obtained. Because the

um c

hest

CK rate in mas

ode is

elected by setting Bit 0 of Address 0x1E.

n slave mo e, external circuitry provides the PCLK signal.

lave-mode PCLK signals can be either synchronous or

nchrono s. The maximum slave-mode PCLK frequency is

PARALLEL PORT PIN FUNCTIONS

ative to the AD6652 CLK. This pin powers up

as an input to avoid possible contentions. Other port outputs

ange on the rising edge of PCLK.

REQ

Active high output, synchronous to PCLK. A logic high on this

s that data is available to be shifted out of the port.

gic hig

igh until all pending data has been

ted out

hig

ronous input. Applying a logic low on this

hibit

el port data shifting. Applying a logic high to

pin wh

is high causes the parallel port to shift out

accor

med data mode. PxACK is

pled o

lling edge of PCLK. Data is shifted out on the

ising

f PCLK after PxACK is sampled. PxACK can

eld hig

ly. In this case, when data becomes

ilable, s

s 1 PCLK cycle after the assertion of

Q (see F

igure 58).

h when

ent on the port output, otherwise

H[1:0

:0]

ese pins

ata in both data modes. In channel

de, thes

it binary number identifying the

rce cha

t data word. In AGC mode, [0]

icates t

= AGC A, 1 = AGC B), and [1]

tes w

is I/Q data (0) or a gain

d (1).

15:0],

lel ou

ts. Contents and format are mode-

endent.

MASTER/SL

l ports operate in either master or

via the port clock control register (Addres

l po

AD6652 c c

divis

maxim

lock rate of the AD6652 is 65 MHz, the hig

ter mode is also 65 MHz. Master m

asy

100 MH

PCLK

Input/output. As an output (master mode), the maximum

frequency is CLK/n, where CLK is the AD6652 clock and n is a

integer divisor 1, 2, 4 or 8. As an input (slave mode), it might be

asynchronous rel

pin indicate

A lo

h value remains h

shif

PxAC

Active

h asynch

pin in

s parall

this

en REQ

data

ding to the program

sam

n the fa

next r

edge o

be h

h continuous

ava

hifting begin

igure 55 to F

PAIQ, PBIQ

Hig

ever I data is pres

low

PAC

], PBCH[1

serve to identify d

e pins form a 2-b

sou

nnel of the curren

ind

he AGC source (0

indica

hether the current data word

wor

PA[

PB[15:0]

Paral

tput data por

dep

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