AD6652BBC datasheet(56/76 Pages) AD

56 / 76 page

AD6652

Rev. 0 | Page 56 of 76

e microport or serial port.

it 6 of the register is the broadcast bit, which determines how

n Bits 5–2, which

n[3:0]), are

] pins. The instruction that

s the CHIP_ID

ss. This

ws up to 16 chips t

the same port and

ory mapped with

allows the

me serial port of a h t processor to configure up to 16 chips.

the broadcast bit is h h, the Instruction[3:0] word allows

ultiple AD6652 chan els and/or chips to be configured

ultaneously indepe

3:0] pins. The

ossible instruction

eful

smart antenna syst

ls listening to

gle antenna or car

ltaneously.

x’s in the commen

ent “don’t

s” in the digital de

t is enabled (Bit 6

h) readback is n

otential for

ternal bus contentio

erefore, if readback is subsequently

ed, the broadcast t should be set low.

its 1–0 of the ACR ar address bits that decode which of the

ur channels are bein

sed. If the instruction bits decode

n access to multiple c nnels, then these bits are ignored. If the

struction decodes an ccess to a subset of chips, then the

bits otherwise d

the channel being accessed.

Instructions,

ruction

Comm

ACCESS CONTROL REGISTER (ACR)

External Address 7

The ACR specifies certain programming characteristics such as

autoincrement or broadcast, which are to be applied to the

incoming instructions, and selects which channel(s) are to be

programmed by th

Bit 7 of this register is the autoincrement bit. If this bit is a 1

then the CAR register, described in the Channel Address

to the channel. This allows blocks of address space such as

coefficient memory to be initialized more efficiently.

Bits 5–2 are interpreted. If broadcast is 0 the

are referred to as instruction bits (Instructio

compared with the

IP_ID[3:0

matche

[3:0] pins determines the acce

allo

o be connected to

mem

out external logic. This also

sim

ndent of the CHIP_ID[

10 p

s are defined in Table 23. This is us

for

ems, where multiple channe

a sin

rier can be configured simu

The

t portion of the table repres

care

et hig

coding. When broadcas

ecause of the p

ot valid b

n. Th

desir

g acces

A[9:8]

etermine

Table 23. Microport

Inst

7:5–2

ent

0000

All chips and all

ls have access.

channe

0001

Channe 0, 1, 2 of all chips have access.

0010

Channe

ps have access.

ls 1, 2, 3 of all chi

0100

All chips get the access.1

1000

All chip

xxx0 have access.1

s with Chip_ID[3:0] =

1001

All chip

xx1 have access.1

s with Chip_ID[3:0] = x

1100

All chip

ID[3:0] = xx00 have access.1

s with Chip_

1101

All chip

_ID[3:0] = xx01 have access.1

s with Chip

1110

All chip

ip_ID[3:0] = xx10 have access.1

s with Ch

1111

All chip

xx11 have access.1

s with Chip_ID[3:0] =

1 A[9:8] bits control which c

f a channel register

autoincrement bit of the

the

gister also contains

BIST (built-in self-test) commands that turn internal test

signals off or on, namely, pseudonoise and negative full-scale

e wav

d 6, explained below.

Bits 0–3

SOFT_SYNC channel enable bits

for each

he fou

h to one

or all of

e bits

selects the indicated channel(s) to be

recipien

a sof

nchronizing pulse—whenever such

signal is

erated

f this register as described

below. A

be used in addition to a soft-sync

signal, if

ired.

Bit 4 is t

ng pulse. Writing this bit to

logic hig

ot-type pulse to trigger the start

hold-of

cted DDC channels according to

Bits 3–0

nnel/Chip Synchronization section

for furth

it also programs

Channel

s Reg

Bit 5 is t

op so

his bit to

logic hig

iate

hop

frequen

old-o

nnels

accordin

Bits

hannel/Chip

Synchro

tion s

mming this bit also programs

the Cha

Addr

Bit 6 co

w the internal input data bus is configured. If

this bit is lo

the ADCs (analog–to-digital converters) are

connect

the

user’s choice—

this is n

l ope

, then the

internal

gna

ll DDC NCOs for BIST

purpose

this

programmed input

choice.

ed in Bit 7 of this

If Bit 7

nal is generated and

made av

f this bit is high, then

the inte al pseudorandom noise generator is enabled and this

data is a

the internal input data bus. The combined

function

its 6 and 7 facilitate BIST functions. Also, in

conjunc

e MISR registers, this allows for detailed

in-syste

testing.

hannel is decoded for access

CHANNEL ADDRESS REGISTER (CAR)

External Address 6

The user writes the 8-bit internal address o

to be programmed in the CAR. If the

ACR is 1, then this value is incremented after every access to

DR0 register, which in turn accesses the location pointed to

this address. The channel address register cannot be read back

while the broadcast bit is set high.

SOFT_SYNC CONTROL REGISTER

External Address 5

The SOFT_SYNC control register is write only. The regist

name is somewhat deceiving in that this re

sin

e, at Bits 7 an

of this register are the

of t

r DDC channels. Writing a logic hig

thes

simply

ts of

t_sync sy

gen

by Bits 4 and 5 o

pin-sy

signal can

des

he start software synchronizi

h initiates a one-sh

f counter of the sele

above. See the Cha

form

er in

Addres

ation. Programming this b

ister 0x82 of each channel.

he h

ftware synchronizing pulse. Writing t

h init

s a one-shot-type pulse to trigger the

cy h

ff counter of the selected DDC cha

g to

3–0 above. See the C

niza

ection. Progra

nnel

ess Register 0x82 of each channel.

nfigures ho

w, then

ed to

DDC NCOs according to the

orma

ration. If this bit is logic high

test si

ls are connected to a

s and

overrides any NCO

The internal test signals are configur

is logic l

, a negative full-scale sig

ailable to the internal data bus. I

vailable to

s of B

tion with th

m chip

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