AD6652BBC datasheet(57/76 Pages) AD

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AD6652

Rev. 0 | Page 57 of 76

PIN_SYNC CONTROL REGISTER

rnal Address 4

he write-only

N_SYNC control register.

its 3–0 of this register are the PIN SYNC_EN control bits.

hese bits can be writt

o by the controller to select any or all

f the external pin syn inputs: A, B, C, and/or D. One pin can

e assigned to all channels, one pin can be assigned to one

nnel, or any combination in between. This register is fully

nfigurable at the channel level (in the channel address register

emory map, 0x88) as to which pin-sync signal is selected. A

sync signal can be

-sync signal, if

red. See Figure 53.

is the start enable

h enables

tates the routin

nal to all the

DC channels. This b enables any pin-sync signals that were

ted by Bits 3–0 ab

-1 multiplexer

ltimately chosen

nc signal that

ntrols the start function. See Figure 53. Programming this bit

o programs the Cha nel Address Register 0x82 of each

nel.

it 5 is the hop enable bit. Writing this bit to logic high enables

al pin-sync signal to all the

n-sync signals that were

synchronization signals. If this

o programs the

External Address 3

e output port control register’s memory map.

control

mode

nel. If the

w, the ch nel operates n

ally. If the bit is high, the

icated channel enters a low-p

er sleep mode. Program-

ng this bit als

rograms the

nnel Address Register 0x82

ach channel.

Bit 5 allows access to the output control port registers. When

this bit

, the

gisters are accessed.

Howeve

hen th

the output

port con

egist

igh, the value in

Externa

dress

mory map for the

output c

ol po

f the normal channel

address

er m

Table 29 in the Output Port

Control Registers

Bit 6–7

e reserv

DATA

Externa

ess 2–0

These r

rm the data registers DR2, DR1, and DR0,

respecti

l in

ual

to or les

al Address 0 is written to, it

triggers

ntern

6652 based on the address

indicate

the A

s, during writes to the

internal

sters,

e written

last. At t

int,

d to the internal memory

indicate in A[9:0

n the opposite

directio Once th

l Address [0] DR0

must be

rst d

internal access.

DR2 is only 4 bits wide. Data written to the upper 4 bits of this

sed via this same location by

access to

or all four

r can overwrite the data in 0x80, if

ep mode is selected when this bit is written logic

Exte

This is t

en t

cha

pin-

used in addition to a soft

desi

Bit 4

r facili

bit. Writing this bit to logic hig

of the external pin-sync sig

selec

ove, to be routed to a 4-to

be the channel’s pin-sy

and u

als

chan

or facilitates the routing of the extern

DDC channels. This bit enables any pi

selected by Bits 3–0 above to be routed to a 4-to-1 multiplexer

and ultimately chosen to be the channel’s pin-sync signal that

controls the Hop function. See Figure 53. Programming this bit

also programs the Channel Address Register 0x82 of each

channel.

Bit 6 is used to ignore repetitive

bit is clear, each PIN_SYNC restarts or frequency hops th

channel. If this bit is set, then only the first occurrence causes

the action to occur. Programming this bit als

Channel Address Register 0x82 of each channel.

Bit 7 is reserved; the bits should be written to Logic 0.

SLEEP CONTROL REGISTER

In addition to sleep mode control, this register also provides

access to th

Bits 3–0

the sleep

of the indicated chan

bit is lo

orm

ind

o p

Cha

of e

Bit 4 is reserved and should be written to Logic 0.

is low

channel address re

r, w

is bit is set high, it allows access to

trol r

ers. When this bit is set h

l Ad

6 (CAR) points to the me

ontr

rt registers instead o

regist

emory map. See

section.

ed and should be written lo

ADDR

S REGISTER

l Addr

egisters fo

vely. Al

ternal data-words have widths that are eq

s than 2 bits. When Extern

an i

al access to the AD

d in

CR and CAR. Thu

regi

External Address [0] DR0 must b

his po

data is transferre

]. Reads are performed i

e address is set, Externa

the fi

ata register read to initiate an

produces only 4 LSBs.

Figure 63 is a block diagram of the memory structure.

CHANNEL ADDRESS REGISTERS (CAR)

0x00–0x7F: Coefficient Memory (CMEM)

This register is the coefficient memory (CMEM) used by the

RCF. It is memory mapped as 128 words by 20 bits. A second

128 words of RAM can be acces

writing Bit 8 of the RCF control register high at Channel

Address 0xA4. The filter calculated always uses the same

coefficients for I and Q. By using memory from both of thes

128 blocks, a filter of up to 160 taps can be calculated. Multiple

filters can be loaded and selected with a single internal

the coefficient offset register at Channel Address 0xA3.

0x80: Channel Sleep Register

This register contains the sleep bit for the channel. It mimics the

programming of Bits 0–3 at External Address 3. External

Address 3 provides simultaneous sleep mode control f

DDC channels. The use

desired. Sle

high.

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