ATSAMB11XR datasheet(26/87 Pages) MICROCHIP

26 / 87 page

7.1.3.5

SPI Controller

See Section SPI Master/Slave Interface.

7.1.3.6

I2C Controller

See Section I2C Master/Slave Interface.

7.1.3.7

SPI-Flash Controller

The AHB SPI-Flash Controller is used to access the internal stacked SPI Flash to access various

instruction/data code required for storing application code, code patches, and OTA images. It supports

several SPI modes including 0, 1, 2, and 3. See Section SPI Flash Master Interface.

7.1.3.8

UART

See Section UART Interface.

7.1.3.9

DMA Controller

Direct Memory Access (DMA) allows certain hardware subsystems to access main system memory

independent of the Cortex-M0 Processor.

The DMA features and benefits are:

•

Supports any address alignment

•

Supports any buffer size alignment

•

Peripheral flow control and peripheral block transfer

•

The following modes are supported:

–

Peripheral to peripheral transfer

–

Memory to memory

–

Memory to peripheral

–

Peripheral to memory

–

•

Interrupts for both TX done and RX done in memory and peripheral mode

•

Scheduled transfers

•

Endianness byte swapping

•

Watchdog timer

•

4-channel operation

•

32-bit Data width

•

AHB MUX (on read and write buses)

•

Command lists support

•

Usage of tokens

7.1.3.10 Nested Vector Interrupt Controller

External interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts. Software can set

the priority of each interrupt. The NVIC and the Cortex-M0 processor core are closely coupled to provide

low-latency interrupt processing and efficient processing of late arriving interrupts.

All NVIC registers are accessible via word transfers and are little endian. Any attempt to read or write a

half-word or byte individually is unpredictable.

The NVIC allows the CPU to be able to individually enable or disable each interrupt source, and hold

each interrupt until it is serviced and cleared by the CPU.

ATSAMB11XR/ZR

Datasheet Preliminary

DS70005342A-page 26

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