ATSAMB11XR datasheet(40/87 Pages) MICROCHIP

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9.5

UART Interface

The ATSAMB11-XR2100A and ATSAMB11-ZR210CA provide Universal Asynchronous Receiver/

Transmitter (UART) interfaces for serial communication. The Bluetooth subsystem contains two UART

interfaces: 2-pin mode for data only, and a 4-pin interface for flow control and data transfer. The UART

interfaces are compatible with the RS-232 standard, where the ATSAMB11-XR2100A and ATSAMB11-

ZR210CA operate as Data Terminal Equipment (DTE). The 4-pin UART has two pins for data (TX and

RX) and two pins for flow control/handshaking: Request To Send (RTS) and Clear To Send (CTS).

Caution: The RTS and CTS are used for hardware flow control. The RTS and CTS pins must

be interfaced to the remote device and hardware flow control must be enabled to guarantee

data integrity.

The pins associated with each UART interfaces can be enabled on several alternative pins by

programming their corresponding pin-MUX control registers (see Table 9-1 and Table 9-2 for available

options).

The UART features the programmable baud rate generation with fractional clock division, which allows

transmission and reception at a wide variety of standard and non-standard baud rates. The Bluetooth

UART input clock is selectable between 26 MHz, 13 MHz, 6.5 MHz, and 3.25 MHz. The clock divider

value is programmable as 13 integer bits and three fractional bits (with 8.0 being the smallest

recommended value for normal operation). This results in the maximum supported baud rate of 26

MHz/8.0 = 3.25 MBd.

The UART can be configured for seven or eight bit operation, with or without parity, with four different

parity types (odd, even, mark, or space), and with one or two stop bits. It also contains RX and TX FIFOs,

which ensure reliable high-speed reception and low software overhead transmission. FIFO size is 4 x 8

for both RX and TX direction. The UART also contains status registers showing the number of received

characters available in the FIFO and various error conditions, and also the ability to generate interrupts

based on these status bits.

An example of UART receiving or transmitting a single packet is shown in Figure 9-2. This example

shows 7-bit data (0x45), odd parity, and two stop bits.

Figure 9-2. Example of UART RX or TX Packet

ATSAMB11XR/ZR

Datasheet Preliminary

DS70005342A-page 40

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