ATSAMB11XR datasheet(14/87 Pages) MICROCHIP

14 / 87 page

Device States

This section includes details on the description and controlling of the Device states.

5.1

Description of Device States

The ATSAMB11-XR2100A and the ATSAMB11-ZR210CA have multiple device states, depending on the

state of the ARM processor and BLE subsystem.

Note: The ARM is required to be powered on, if the BLE subsystem is active.

•

BLE_On_Transmit – Device is actively transmitting a BLE signal.

•

BLE_On_Receive – Device is in active receive state.

•

MCU_Only – Device has ARM processor powered-on and BLE subsystem powered-down.

•

Ultra_Low_Power – BLE subsystem and ARM processor are powered-down.

•

Power_Down – Device core supply off.

5.1.1

Controlling the Device States

The following pins are used to switch between the main device states:

•

C_EN – used to enable PMU

•

VDDIO – I/O supply voltage from an external power supply

•

AO_GPIO_0 - can be used to control the device from entering/exiting Ultra_Low_Power mode

To be in the Power_Down state, the VDDIO supply must be turned on and the C_EN must be maintained

at logic low (at GND level). To switch between the Power_Down state and the MCU_Only state, C_EN

must be maintained at logic high (VDDIO voltage level). Once the device is in the MCU_Only state, all

other state transitions are controlled entirely by software. When VDDIO supply is turned off and C_EN is

in logic low, the chip is powered off with no leakage.

When VDDIO supply is turned off, voltage cannot be applied to the ATSAMB11-XR2100A pins, as each

pin contains an ESD diode from the pin to supply. This diode turns on, when a voltage higher than one

diode-drop is supplied to the pin.

If voltage is applied to the signal pads while the chip is in a low power state, the VDDIO supply must be

on so the Power_Down state is used. Similarly, to prevent the pin-to-ground diode from turning on, do not

apply a voltage that is more than one diode-drop below ground to any pin.

The AO_GPIO_0 pin can be used to control the device from entering and exiting Ultra_Low_Power mode.

When AO_GPIO_0 is maintained in logic high state, the device will not enter Ultra_Low_Power mode.

When the AO_GPIO_0 is maintained in logic low, the device will enter Ultra_Low_Power mode provided

there are no BLE events to be handled. To achieve the lowest power consumption in Ultra_Low_Power

mode, AO_GPIO_0 pin must be held in logic low.

5.2

Power Sequences

The power sequences and timing parameters for the ATSAMB11-XR2100A and ATSAMB11-ZR210CA,

are illustrated below.

ATSAMB11XR/ZR

Datasheet Preliminary

DS70005342A-page 14

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