CYUSB302X datasheet(5/34 Pages) CYPRESS

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Document Number: 001-55190 Rev. *L

Page 5 of 34

CYUSB302x

Power

SD3 has the following main groups of power supply domains:

■ IO_VDDQ: This refers to a group of independent supply

domains for digital I/Os. The voltage level on these supplies

are 1.8 V to 3.3 V. SD3 provides six independent supply

domains for digital I/Os listed as follows:

❐ S0VDDQ: S0-Port (for SD/MMC) I/O Power Supply Domain

❐ S1VDDQ: S1-Port (for SD/MMC) I/O Power Supply Domain

❐ S2VDDQ: S2-Port (GPIO) Power Supply Domain

❐ VIO4: S1-Port GPIO[53:57]/O Power Supply Domain (these

pins support MMC’s high nibble data line - D[7:4] on S1-Port)

❐ VIO5: I2C Power Supply Domain (supports 1.2 V to 3.3 V)

❐ CVDDQ: Clock Power Supply Domain

■ VDD: This is the supply voltage for the logic core. The nominal

supply voltage level is 1.2 V. This supplies the core logic

circuits. The same supply must also be used for the following:

❐ AVDD: This is the 1.2-V supply for the PLL, crystal oscillator

and other core analog circuits

❐ U3TXVDDQ/U3RXVDDQ: These are the 1.2-V supply volt-

ages for the USB 3.0 interface.

■ VBATT/VBUS: This is the 3.2-V to 6-V battery power supply

for the USB I/O and analog circuits. This supply powers the

USB transceiver through SD3’s internal voltage regulator.

VBATT is internally regulated to 3.3 V.

Power Modes

SD3 supports the following power modes:

■ Normal mode: This is the full-functional operating mode. In this

mode the internal CPU clock and the internal PLLs are enabled.

Normal operating power consumption does not exceed the sum

of ICC_CORE max and ICC_USB max (see Table 9 on page 15

for current consumption specifications).

The I/O power supplies (S0VDDQ, S1VDDQ, VIO4, and VIO5)

may be turned off when the corresponding interface is not in use.

S2VDDQ cannot be turned off at any time if the S2-Port is used

in the application.

■ SD3 supports four low-power modes (see Table 6 on page 5):

❐ Suspend mode with USB 3.0 PHY enabled (L1 mode)

❐ Suspend mode with USB 3.0 PHY disabled (L2 mode)

❐ Standby mode (L3 mode)

❐ Core power-down mode (L4 mode)

Table 6. Entry and Exit Methods for Low-Power Modes

Low Power Mode

Characteristics

Methods of Entry

Methods of Exit

Suspend mode with

USB 3.0 PHY Enabled

(L1 mode)

■ The power consumption in this mode does

not exceed ISB1

■ USB 3.0 PHY is enabled and is in U3 mode

(one of the suspend modes defined by the

USB 3.0 specification). This one block alone

operates with its internal clock while all other

clocks are shut down

■ All I/Os maintain their previous state

■ Power supply for the wakeup source and

core power must be retained. All other

power domains can be turned on/off individ-

ually

■ The states of the configuration registers,

buffer memory and all internal RAM are

maintained

■ All transactions must be completed before

SD3 enters Suspend mode (state of

outstanding transactions are not preserved)

■ The firmware resumes operation from

where it was suspended (except when

woken up by RESET# assertion) because

the program counter does not reset

■ Firmware executing on the core can put

SD3 into suspend mode. For example,

on USB suspend condition, firmware

may decide to put SD3 into suspend

mode

■ D+ transitioning to low or high

■ D– transitioning to low or high

■ Resume condition on SSRX +/-

■ Detection of VBUS

■ Assertion of GPIO[17]

■ Assertion of RESET#

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