CYUSB302X datasheet(6/34 Pages) CYPRESS

6 / 34 page

Document Number: 001-55190 Rev. *L

Page 6 of 34

CYUSB302x

Suspend mode with

USB 3.0 PHY disabled

(L2 mode)

■ The power consumption in this mode does

not exceed ISB2

■ USB 3.0 PHY is disabled and the USB

interface is in suspend mode

■ The clocks are shut off. The PLLs are

disabled

■ All I/Os maintain their previous state

■ USB interface maintains the previous state

■ Power supply for the wakeup source and

core power must be retained. All other

power domains can be turned on/off individ-

ually

■ The states of the configuration registers,

buffer memory, and all internal RAM are

maintained

■ All transactions must be completed before

SD3 enters Suspend mode (state of

outstanding transactions are not preserved)

■ The firmware resumes operation from

where it was suspended (except when

woken up by RESET# assertion) because

the program counter does not reset

■ Firmware executing on the core can put

SD3 into suspend mode. For example,

on USB suspend condition, firmware

may decide to put SD3 into suspend

mode

■ D+ transitioning to low or high

■ D– transitioning to low or high

■ Resume condition on SSRX +/-

■ Detection of VBUS

■ Assertion of GPIO[17]

■ Assertion of RESET#

Standby Mode (L3

mode)

■ The power consumption in this mode does

not exceed ISB3

■ All configuration register settings and

program/data RAM contents are preserved.

However, data in the buffers or other parts

of the data path, if any, is not guaranteed.

Therefore, the external processor should

take care that needed data is read before

putting SD3 into this Standby Mode

■ The program counter is reset after waking

up from Standby

■ GPIO pins maintain their configuration

■ Crystal oscillator is turned off

■ Internal PLL is turned off

■ USB transceiver is turned off

■ Core is powered down. Upon wakeup, the

core re-starts and runs the program stored

in the program/data RAM

■ Power supply for the wakeup source and

core power must be retained. All other

power domains can be turned on/off individ-

ually

■ Firmware executing on the core or

external processor configures the appro-

priate register

■ Detection of VBUS

■ Assertion of GPIO[17]

■ Assertion of RESET#

Core Power Down

Mode (L4 mode)

■ The power consumption in this mode does

not exceed ISB4

■ Core power is turned off

■ All buffer memory, configuration registers

and the program RAM do not maintain state.

It is necessary to reload the firmware on

exiting from this mode

■ In this mode, all other power domains can

be turned on/off individually

■ Turn off VDD

■ Reapply VDD

■ Assertion of RESET#

Table 6. Entry and Exit Methods for Low-Power Modes (continued)

Low Power Mode

Characteristics

Methods of Entry

Methods of Exit

CYUSB302X Arkusz danych(PDF) 6 Page - Cypress Semiconductor

CYUSB302X Arkusz danych(HTML) 6 Page - Cypress Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Arkusz danych Pobierz

Link URL