STA003T datasheet(12/32 Pages) STMICROELECTRONICS

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4.1 - STA003T REGISTERS DESCRIPTION

The STA003T device includes 128 I

2C registers.

In this document, only the user-oriented registers

are described. The undocumented registers are

reserved. These registers must never be ac-

cessed (in Read or in Write mode). The Read-

Only registers must never be written.

The following table describes the meaning of the

abbreviations used in the I2C registers descrip-

tion:

Symbol

Comment

Not Applicable

UND

Undefined

No Charge

Read Only

Write Only

R/W

Read and Write

R/WS

Read, Write in specific mode

VERSION

Address: 0x00

Type: RO

MSB

LSB

The VERSION register is read-only and it is used

to identify the IC on the application board.

IDENT

Address: 0x01

Type: RO

Software Reset: 0xAC

Hardware Reset: 0xAC

MSB

LSB

10101

100

IDENT is a read-only register and is used to iden-

tify the IC on an application board. IDENT always

has the value "0xAC"

PLLCTL

Address: 0x05

Type: R/W

Software Reset: 0x21

Hardware Reset: 0x21

MSB

LSB

XTO_

BUF

XTOD

OCLK

SYS2O

CLK

PPLD

XTI2DS

PCLK

XTI2O

CLK

UPD_F

RAC

UPD_FRAC: when is set to 1, updates FRAC in

the switching circuit. It is set to 1 after autoboot.

XTI2OCLK: when is set to 1, uses the XTI as in-

put of the divider X instead of VCO output. It is

set to 0 on HW reset.

XTI2DSPCLK: when is set to 1, uses the XTI as

input of the divider S instead of VCO output. It is

set to 0 on HW reset.

PLLDIS: when set to 1, the VCO output is dis-

abled. It is set to 0 on HW reset.

SYS2OCLK: when is set to 1, the OCLK fre-

quency is equal to the system frequency. It is

useful for testing. It is set to 0 on HW reset.

OCLKEN: when is set to 1, the OCLK pad is en-

able as output pad. It is set to 1 on HW reset.

XTODIS: when is set to 1, the XTO pad is dis-

abled. It is set to 0 on HW reset.

XTO_BUF: when this bit is set, the pin nr. 28

(VDD_5/CLK_OUT) is enabled as buffered (4mA)

master clock output (CLK_OUT). It is set to 0 af-

ter autoboot.

PLLCTL_M

Address: 0x06

Type: R/W

Software Reset: 0x0C

Hardware Reset: 0x0C

PLLCTL_N

Address: 0x07

Type: R/W

Software Reset: 0x00

Hardware Reset: 0x00

The M and N registers are used to configure the

STA003T PLL by DSP embedded software.

M and N registers are R/W type but they are

completely controlled, on STA003T, by DSP soft-

ware.

STA003T

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