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STA003T Arkusz danych(PDF) 21 Page - STMicroelectronics |
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STA003T Arkusz danych(HTML) 21 Page - STMicroelectronics |
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21 / 32 page ![]() PCMCROSS Address: 0x56 Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 Description X X X X X X 0 0 Left channel is mapped on the left output. Right channel is mapped on the Right output X X X X X X 0 1 Left channel is duplicated on both Output channels. X X X X X X 1 0 Right channel is duplicated on both Output channels X X X X X X 1 1 Right and Left channels are toggled The default configuration for this register is ’0x00’. ANCILLARY DATA BUFFER Address: 0x59 - 0x5D Type: RO Software Reset: 0x00 Hardware Reset: 0x00 STA003T can extract max 56 bytes/MPEG frame. To know the number of A.D. bits available every MPEG frame, the ANCCOUNT_L and ANC- COUNT_H registers (0x41 and 0x42) have to be read. The buffer dimension is 5 bytes, written by STA003T core in sequential order. The timing in- formation to read the buffer can be obtained by reading the FRAME_CNT registers (0x67 - 0x69). To fill up the buffer with a new 5-bytes slot, the STA003T waits until a CMD_INTERRUPT regis- ter is written by the master. MFSDF (X) Address: 0x61 Type: R/W Software Reset: 0x0F Hardware Reset: 0x0F MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 X X X M4 M3M2M1M0 The register contains the values for PLL X divider (see Fig. 6). The value is changed by the internal STA003T Core, to set the clock frequencies, according to the incoming bitstream. This value can be even set by the user to select the PCM interface con- figuration. The VCO output frequency is divided by (X+1). DAC_CLK_MODE Address: 0x63 Type: RW Software Reset: 0x00 Hardware Reset: 0x00 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 XXXXXXX MODE This register is used to select the operating mode for OCLK clock signal. If it is set to ’1’, the OCLK frequency is fixed, and it is mantained to the value fixed by the user even if the sampling frequency of the incoming bit- stream changes. If the MODE flag is set to ’0’, the OCLK frequency changes, and can be set to (512, 384, 256) * Fs. The default configuration for this mode is 256 * Fs. When this mode is selected, the default OCLK frequency is 12.288 MHz. STA003T 21/32 |
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