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LPC802 Arkusz danych(PDF) 26 Page - NXP Semiconductors |
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LPC802 Arkusz danych(HTML) 26 Page - NXP Semiconductors |
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26 / 83 page ![]() LPC802 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 1.6 — 27 April 2018 26 of 83 NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller 9.21 CRC engine The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings supports several CRC standards commonly used. To save system power and bus bandwidth, the CRC engine supports DMA transfers. 9.21.1 Features • Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32. – CRC-CCITT: x16 + x12 + x5 + 1 – CRC-16: x16 + x15 + x2 + 1 – CRC-32: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 • Bit order reverse and 1’s complement programmable setting for input data and CRC sum. • Programmable seed number setting. • Supports CPU PIO or DMA back-to-back transfer. • Accept any size of data width per write: 8, 16 or 32-bit. – 8-bit write: 1-cycle operation. – 16-bit write: 2-cycle operation (8-bit x 2-cycle). – 32-bit write: 4-cycle operation (8-bit x 4-cycle). |
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