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LPC802 Arkusz danych(PDF) 38 Page - NXP Semiconductors |
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LPC802 Arkusz danych(HTML) 38 Page - NXP Semiconductors |
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38 / 83 page ![]() LPC802 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 1.6 — 27 April 2018 38 of 83 NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller [1] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. [2] Maximum/minimum voltage above the maximum operating voltage (see Table 12) and below ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device. [3] Applies to all 5 V tolerant I/O pins except the 3 V tolerant pin PIO0_7. [4] Including the voltage on outputs in 3-state mode. [5] VDD present or not present. [6] An ADC input voltage above 3.6 V can be applied for a short time without leading to immediate, unrecoverable failure. Accumulated exposure to elevated voltages at 4.6 V must be less than 106 s total over the lifetime of the device. Applying an elevated voltage to the ADC inputs for a long time affects the reliability of the device and reduces its lifetime. [7] If the comparator is configured with the common mode input VIC = VDD, the other comparator input can be up to 0.2 V above or below VDD without affecting the hysteresis range of the comparator function. [8] It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin. [9] Dependent on package type. [10] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. [11] JEDEC (4.5 in 4 in); still air. [12] Single layer (4.5 in 3 in); still air. Ptot(pack) total power dissipation (per package) TSSOP16, based on package heat transfer, not device power consumption [11] -0.29 W TSSOP16, based on package heat transfer, not device power consumption [12] -0.22 W TSSOP20, based on package heat transfer, not device power consumption [11] -0.36 W TSSOP20, based on package heat transfer, not device power consumption [12] -0.26 W HVQFN33, based on package heat transfer, not device power consumption [11] -0.91 W HVQFN33, based on package heat transfer, not device power consumption [12] -0.34 W WLCSP16, based on package heat transfer, not device power consumption [11] -0.65 W WLCSP16, based on package heat transfer, not device power consumption [12] -0.27 W Vesd electrostatic discharge voltage human body model; all pins [10] - 2000 V Table 9. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit |
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