MPC7445 datasheet(48/64 Pages) FREESCALE

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MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1

Freescale Semiconductor

System Design Information

The MPC7455 generates the clock for the external L3 synchronous data SRAMs by dividing the core clock

frequency of the MPC7455. The core-to-L3 frequency divisor for the L3 PLL is selected through the L3_CLK bits

of the L3CR register. Generally, the divisor must be chosen according to the frequency supported by the external

RAMs, the frequency of the MPC7455 core, and timing analysis of the circuit board routing. Table 18 shows various

example L3 clock frequencies that can be obtained for a given set of core frequencies.

9.2 PLL Power Supply Filtering

The AVDD power signal is provided on the MPC7455 to provide power to the clock generation PLL. To ensure

stability of the internal clock, the power supplied to the AVDD input signal should be filtered of any noise in the 500

kHz to 10 MHz resonant frequency range of the PLL. A circuit similar to the one shown in Figure 24 using surface

mount capacitors with minimum effective series inductance (ESL) is recommended.

The circuit should be placed as close as possible to the AVDD pin to minimize noise coupled from nearby circuits.

It is often possible to route directly from the capacitors to the AVDD pin, which is on the periphery of the 360 CBGA

footprint and very close to the periphery of the 483 CBGA footprint, without the inductance of vias.

Table 18. Sample Core-to-L3 Frequencies

Core Frequency

(MHz)

÷2

÷2.5

÷3

÷3.5

÷4

÷5

÷6

500

250

200

167

143

125

100

533

266

213

178

152

133

107

550

275

220

183

157

138

110

600

300

240

200

171

150

120

100

6502

325

260

217

186

163

130

108

6662

333

266

222

190

167

133

111

7002

350

280

233

200

175

140

117

7332

367

293

244

209

183

147

122

8002

400

320

266

230

200

160

133

8672

433

347

289

248

217

173

145

9332

467

373

311

266

233

187

156

10002

500

400

333

285

250

200

166

Notes:

1. The core and L3 frequencies are for reference only. Note that maximum L3 frequency is design dependent. Some

examples may represent core or L3 frequencies which are not useful, not supported, or not tested for the MPC7455;

see Section 5.2.3, “L3 Clock AC Specifications,” for valid L3_CLK frequencies and for more information regarding

the maximum L3 frequency. Shaded cells do not comply with Table 10.

2. These core frequencies are not supported by all speed grades; see Table 8.

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