JS28F256P30T85 datasheet(80/102 Pages) INTEL

80 / 102 page

1-Gbit P30 Family

April 2005

Intel StrataFlash® Embedded Memory (P30)

Datasheet

Order Number: 306666, Revision: 001

Figure 36.

Write State Machine—Next State Table (Sheet 3 of 6)

Setup

Busy

Setup

Busy

Suspend

Setup

BP Load 1

BP Load 2

Confirm

BP Busy

Suspend

Setup

Busy

Suspend

Erase

Word

Program

OTP

Ready

Current Chip

State

(7)

Lock/CR Setup

OTP

Setup

(4)

Lock

Block

Confirm

(8)

Lock-Down

Block

Confirm

(8)

Write RCR

Confirm

(8)

Block Address

(?WA0)

Illegal Cmds or

BEFP Data

(1)

(C0H)

(01H)

(2FH)

(03H)

(XXXXH)

(all other codes)

OTP

Setup

Ready

(Lock

Error)

Ready

(Lock

Block)

Ready

(Lock Down

Blk)

Ready

(Set CR)

Ready

N/A

Ready

Ready (BP Load 2 BP Load 2

Ready

BP Confirm if

Data load into

Program Buffer is

complete; ELSE

BP Load 2

Ready (Error)

(Proceed if

unlocked or lock

error)

Ready (Error)

Ready

N/A

BP Confirm if Data load into Program Buffer is

complete; ELSE BP load 2

Ready (Error)

BP Busy

Erase Busy

Word Program Suspend

BP Load 1

BP Load 2

OTP Busy

Word Program Busy

WSM

Operation

Completes

Command Input to Chip and resulting Chip Next State

N/A

Ready (Lock Error)

Ready

BP Suspend

Ready (Error)

Erase Suspend

N/A

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