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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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JS28F256P30T85 Arkusz danych(PDF) 37 Page - Intel Corporation |
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JS28F256P30T85 Arkusz danych(HTML) 37 Page - Intel Corporation |
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37 / 102 page  1-Gbit P30 Family Datasheet Intel StrataFlash® Embedded Memory (P30) April 2005 Order Number: 306666, Revision: 001 37 R101 tAVVH Address setup to ADV# high 10 - ns 1 R102 tELVH CE# low to ADV# high 10 - ns R103 tVLQV ADV# low to output valid Vcc = 1.8 V – 2.0 V -85 ns Vcc = 1.7 V – 2.0 V -88 R104 tVLVH ADV# pulse width low 10 - ns R105 tVHVL ADV# pulse width high 10 - ns R106 tVHAX Address hold from ADV# high 9 - ns 1,4 R108 tAPA Page address access - 25 ns 1 R111 tphvh RST# high to ADV# high 30 - ns Clock Specifications R200 fCLK CLK frequency - 40 MHz 1,3,6 R201 tCLK CLK period 25 - ns R202 tCH/CL CLK high/low time 5 - ns R203 tFCLK/RCLK CLK fall/rise time - 3 ns Synchronous Specifications R301 tAVCH/L Address setup to CLK 9 - ns 1 R302 tVLCH/L ADV# low setup to CLK 9 - ns R303 tELCH/L CE# low setup to CLK 9 - ns R304 tCHQV / tCLQV CLK to output valid - 20 ns R305 tCHQX Output hold from CLK 3 - ns 1,5 R306 tCHAX Address hold from CLK 10 - ns 1,4,5 R307 tCHTV CLK to WAIT valid - 20 ns 1,5 R311 tCHVL CLK Valid to ADV# Setup 3 - ns 1 R312 tCHTX WAIT Hold from CLK 3 - ns 1,5 NOTES: 1. See Figure 13, “AC Input/Output Reference Waveform” on page 33 for timing measurements and max allowable input slew rate. 2. OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV. 3. Sampled, not 100% tested. 4. Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specification is satisfied first. 5. Applies only to subsequent synchronous reads. 6. See your local Intel representative for designs requiring higher than 40 MHz synchronous operation. Table 17. AC Read Specifications for 256/512-Mbit and 1-Gbit Densities (Sheet 2 of 2) Num Symbol Parameter Speed Min Max Unit Notes |
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