JS28F256P30T85 datasheet(51/102 Pages) INTEL

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1-Gbit P30 Family

Datasheet

Intel StrataFlash® Embedded Memory (P30)

April 2005

Order Number: 306666, Revision: 001

9.3

Command Definitions

Valid device command codes and descriptions are shown in Table 21.

Protection

Program Protection Register

Write

PRA

0xC0

Write

PRA

Program Lock Register

Write

LRA

0xC0

Write

LRA

LRD

Configuration

Program Read Configuration

Write

RCD

0x60

Write

RCD

0x03

Notes:

First command cycle address should be the same as the operation’s target address.

DBA = Device Base Address (NOTE: needed for 2 or more die stacks)

IA = Identification code address offset.

QA = CFI Query address offset.

WA = Word address of memory location to be written.

BA = Address within the block.

PRA = Protection Register address.

LRA = Lock Register address.

RCD = Read Configuration Register data on A[15:0].

ID = Identifier data.

QD = Query data on DQ[15:0].

SRD = Status Register data.

WD = Word data.

N = Word count of data to be loaded into the write buffer.

PD = Protection Register data.

LRD = Lock Register data.

The second cycle of the Buffered Program Command is the word count of the data to be loaded into the write buffer. This

is followed by up to 32 words of data.Then the confirm command (0xD0) is issued, triggering the array programming

operation.

The confirm command (0xD0) is followed by the buffer data.

Table 20.

Command Bus Cycles (Sheet 2 of 2)

Mode

Command

Bus

Cycles

First Bus Cycle

Second Bus Cycle

Oper

Addr(1)

Data(2)

Oper

Addr(1)

Data(2)

Table 21.

Command Codes and Definitions (Sheet 1 of 2)

Mode

Code

Device Mode

Description

Read

0xFF

Read Array

Places the device in Read Array mode. Array data is output on DQ[15:0].

0x70

Read Status Register

Places the device in Read Status Register mode. The device enters this mode

after a program or erase command is issued. Status Register data is output on

DQ[7:0].

0x90

Read Device ID

or Configuration

Places device in Read Device Identifier mode. Subsequent reads output

manufacturer/device codes, Configuration Register data, Block Lock status, or

Protection Register data on DQ[15:0].

0x98

Read Query

Places the device in Read Query mode. Subsequent reads output Common

Flash Interface information on DQ[7:0].

0x50

Clear Status Register

The WSM can only set Status Register error bits. The Clear Status Register

command is used to clear the SR error bits.

Write

0x40

Word Program Setup

First cycle of a 2-cycle programming command; prepares the CUI for a write

operation. On the next write cycle, the address and data are latched and the

WSM executes the programming algorithm at the addressed location. During

program operations, the device responds only to Read Status Register and

Program Suspend commands. CE# or OE# must be toggled to update the

Status Register in asynchronous read. CE# or ADV# must be toggled to update

the Status Register Data for synchronous Non-array reads. The Read Array

command must be issued to read array data after programming has finished.

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