JS28F256P30T85 datasheet(88/102 Pages) INTEL

88 / 102 page

1-Gbit P30 Family

April 2005

Intel StrataFlash® Embedded Memory (P30)

Datasheet

Order Number: 306666, Revision: 001

Figure 43.

BEFP Flowchart

NOTES:

1. First-word address to be program med within the target block must be aligned on a write -buffer boundary .

2. Write-buffer contents are program m ed sequentially to the flash array starting at the first word address (WSM internally increm ents addressing ).

BEFP Exit

Repeat for subsequent blocks ;

After BEFP exit, a full Status Register check can

determ ine if any program error occurred ;

See full Status Register check procedure in the

Word Program flowchart.

Write 0xFF to enter Read Array state .

Standby

Read

Bus

State

Operation

Status

Check

Exit

Status

Comm ents

Data = Status Register Data

Address = 1

st Word Addr.

Check SR[7]:

0 = Exit Not Com pleted

1 = Exit Com pleted

BEFP Setup

Comments

Bus

State

Operation

Write

(Note 1)

BEFP

Setup

Write

BEFP

Confirm

Read

Status

Standby

BEFP

Setup

Done?

Write

Unlock

Block

Data = 0x80 @ 1

st Word

Address

Data = 0x80 @ 1

st Word

Address

Data = Status Register Data

Address = 1

st Word Addr.

Check SR[7]:

0 = BEFP Ready

1 = BEFP Not Ready

VPPH applied to VPP

Standby

Error

Condition

Check

If SR [7] is set, check:

SR[3] set = VPP Error

SR[1] set = Locked Block

No (SR[0]=1)

Write Data @ 1

W ord Address

Last

Data?

W rite 0xFFFF,

Address Not within

Current Block

Program

Done?

Read

Status Reg.

Yes (SR[0]=0)

No (SR[7]=0)

Full Status Check

Procedure

Program

Complete

Read

Status Reg.

BEFP

Exited?

Yes (SR[7]=1)

Start

Write 80h @

st Word Address

VPP applied

Block Unlocked

Write D0h @

st Word Address

BEFP Setup

Done?

Read

Status Reg.

No (SR[7]=1)

Exit

Program & Verify Phase

Exit Phase

Setup Phase

BUFFERED ENHANCED FACTORY PROGRAMMING (BEFP) PROCEDURE

Check

X = 32?

Initialize Count:

X = 0

Increm ent Count:

X = X+1

Check VPP, Lock

errors (SR[3,1])

Yes (SR[7]=0)

BEFP Setup delay

Data Stream

Ready?

Read

Status Reg.

Yes (SR[0]=0)

No (SR[0]=1)

BEFP Program & Verify

Comments

Bus

State

Write

(note 2)

Load

Buffer

Standby

Increm ent

Count

Standby

Initialize

Count

Data = Data to Program

Address = 1

st Word Addr.

X = X+1

X = 0

Read

Status

Standby

Program

Done?

Data = Status Reg. Data

Address = 1

st Word Addr.

Check SR [0]:

0 = Program Done

1 = Program in Progress

Write

Exit Prog &

Verify Phase

Data = 0xFFFF @ address

not in current block

Standby

Last

Data?

No = Fill buffer again

Yes = Exit

Standby

Buffer

Full?

X = 32?

Yes = Read SR[0]

No = Load Next Data Word

Read

Standby

Status

Data Stream

Ready?

Data = Status Register Data

Address = 1

st Word Addr.

Check SR [0]:

0 = Ready for Data

1 = Not Ready for Data

Operation

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