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P5021 Arkusz danych(PDF) 21 Page - NXP Semiconductors

Numer części P5021
Szczegółowy opis  P5021 QorIQ Integrated Processor Data Sheet
PDF  155 Pages
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Producent  NXP [NXP Semiconductors]
Strona internetowa  http://www.nxp.com
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P5021 Arkusz danych(HTML) 21 Page - NXP Semiconductors

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Pin assignments and reset states
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
21
SDHC_DAT0
Data
AP24
I/O
CVDD
—
SDHC_DAT1
Data
AT24
I/O
CVDD
—
SDHC_DAT2
Data
AM23
I/O
CVDD
—
SDHC_DAT3
Data
AG22
I/O
CVDD
—
SDHC_DAT4/SPI_CS0
Data
AN29
I/O
CVDD
26, 31
SDHC_DAT5/SPI_CS1
Data
AJ28
I/O
CVDD
26, 31
SDHC_DAT6/SPI_CS2
Data
AR29
I/O
CVDD
26, 31
SDHC_DAT7/SPI_CS3
Data
AM29
I/O
CVDD
26, 31
SDHC_CLK
Host to Card Clock
AL23
O
CVDD
—
SDHC_CD/IIC3_SCL/GPIO16
Card Detection
AK13
I
OVDD
26,27,31
SDHC_WP/IIC3_SDA/GPIO17
Card Write Protection
AM14
I
OVDD
26,27,31
eSPI
SPI_MOSI
Master Out Slave In
AT29
I/O
CVDD
—
SPI_MISO
Master In Slave Out
AH28
I
CVDD
—
SPI_CLK
eSPI clock
AK29
O
CVDD
—
SPI_CS0/SDHC_DAT4
eSPI chip select
AN29
O
CVDD
26
SPI_CS1/SDHC_DAT5
eSPI chip select
AJ28
O
CVDD
26
SPI_CS2/SDHC_DAT6
eSPI chip select
AR29
O
CVDD
26
SPI_CS3/SDHC_DAT7
eSPI chip select
AM29
O
CVDD
26
IEEE 1588
TSEC_1588_CLK_IN
Clock In
AL35
I
LVDD
—
TSEC_1588_TRIG_IN1
Trigger In 1
AL36
I
LVDD
—
TSEC_1588_TRIG_IN2/EC1_RX_ER
Trigger In 2
AK36
I
LVDD
—
TSEC_1588_ALARM_OUT1
Alarm Out 1
AJ36
O
LVDD
—
TSEC_1588_ALARM_OUT2/EC1_COL/GPIO30
Alarm Out 2
AK35
O
LVDD
26
TSEC_1588_CLK_OUT
Clock Out
AM30
O
LVDD
—
TSEC_1588_PULSE_OUT1
Pulse Out1
AL30
O
LVDD
—
TSEC_1588_PULSE_OUT2/EC1_CRS/GPIO31
Pulse Out2
AJ34
O
LVDD
26
Ethernet Management interface 1
EMI1_MDC
Management Data Clock
AJ33
O
LVDD
—
EMI1_MDIO
Management Data In/Out
AL32
I/O
LVDD
—
Ethernet Management interface 2
EMI2_MDC
Management Data Clock
AK30
O
1.2 V
2, 18, 22
Table 1. Pins listed by bus (continued)
Signal
Signal description
Package
pin number
Pin
type
Power
supply
Notes



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