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ADP1034ACPZ-1-R7 Arkusz danych(PDF) 30 Page - Analog Devices |
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ADP1034ACPZ-1-R7 Arkusz danych(HTML) 30 Page - Analog Devices |
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30 / 41 page ![]() Data Sheet ADP1034 THEORY OF OPERATION analog.com Rev. 0 | 30 of 41 Figure 80. SPI Isolators Timing Diagram The MI, SCK, and SI outputs are also tristated when MSS is high (see Table 15) to allow a more flexible design and to avoid the requirement for external multiplexing of MI in a multichannel sys- tem. Figure 81 shows how the SPI busses from multiple ADP1034 devices can be connected together. Table 15. SPI MSS Gating Parameter MSS High MSS Low SSS High Low SCK Tristate MCK SI Tristate MO MI Tristate SO Connect a pull-up or pull-down resistor to MI, SCK, and SI to pull these pins to the desired logic state when MSS is high. Figure 81. Multichannel SPI Muxing Scheme |
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