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MB90F474LPF Arkusz danych(PDF) 77 Page - fujitsu semiconductor |
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MB90F474LPF Arkusz danych(HTML) 77 Page - fujitsu semiconductor |
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77 / 118 page  MB90470 Series 77 21. µµµµDMA µDMA is the simplified DMA which has the equivalent function to EI2OS function µDMA has DMA transfer channel which consists of 16 channels and has the following functions. • Automatic data transfer between peripheral resources (I/O) and memory. • CPU program executing stops dring DMA operation. • Selectable for address transfer increase/decrease . • DMA transfer control is done at DMA enable register, DMA stop status register, DMA status register and descriptor. • Stop request stops DMA transfer from resources. • After DMA transfer, flag is set to bit corresponding to DMA status register transfer stop channel and stop interrupt is output to interrupt controller. (1) Register List DMA enable register DMA enable register DMA stop status register DMA status register DMA status register bit Initial value DERH : 0000ADH 0 0 0 0 0 0 0 0B bit Initial value DERL : 0000ACH 0 0 0 0 0 0 0 0B bit Initial value DSSR : 0000A4H 0 0 0 0 0 0 0 0B bit Initial value DSRH : 00009DH 0 0 0 0 0 0 0 0B bit Initial value DSRL : 00009CH 0 0 0 0 0 0 0 0B (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 15 14 13 12 11 10 9 8 EN14 (R/W) EN15 EN13 EN12 EN11 EN10 EN9 EN8 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 76 5 4 3 2 1 0 EN6 (R/W) EN7 EN5 EN4 EN3 EN2 EN1 EN0 76 5 4 3 2 1 0 STP6 STP7 STP5 STP4 STP3 STP2 STP1 STP0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 15 14 13 12 11 10 9 8 DE14 DE15 DE13 DE12 DE11 DE10 DE9 DE8 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) ( R/W ) ( R/W ) ( R/W ) (R/W) (R/W) (R/W) (R/W) 76 5 4 3 2 1 0 DE6 ( R/W ) DE7 DE5 DE4 DE3 DE2 DE1 DE0 |
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