BLUENRG-332VC datasheet(15/67 Pages) STMICROELECTRONICS

15 / 67 page

2.9

Clock management

Three different clock sources may be used to drive the system clock of the BlueNRG-LPS:

•

HSI: high speed internal 64 MHz RC oscillator

•

PLL64M: 64 MHz PLL clock

•

HSE: high speed 32 MHz external crystal

The BlueNRG-LPS also has a low speed clock tree used by some timers in the radio, RTC, IWDG and LPUART.

Three different clock sources can be used for this low speed clock tree:

•

Low speed internal (LSI): low speed and low drift internal RC with a fixed frequency between 24 kHz and

49 kHz depending on the sample

•

Low speed external (LSE) from:

–

An external crystal 32.768 kHz

–

A single-ended 32.738 kHz input signal

•

A 32 kHz clock derived from dividing HSI or HSE. In this case, the slow clock is not available in

DEEPSTOP low-power mode

By default, after a system reset, all low speed sources are OFF.

Both the activation and the selection of the slow clock are relevant during DEEPSTOP mode and at wakeup as

slow clock generates a clock for the timers involved in wake-up event generation.

The HSI and the PLL64M clocks are provided by the same analog block called RC64MPLL. The 64 MHz clock

output by this block can be:

•

A non-accurate clock when no external XO provides an input clock to this block (HSI)

•

An accurate clock when the external XO provides the 32 MHz and once its internal PLL is locked (PLL64M)

After reset, the CLK_SYS is divided by four to provide 16 MHz to the whole system (CPU, DMA, memories and

peripherals).

BlueNRG-LPS

Clock management

DS13819 - Rev 4

page 15/67

BLUENRG-332VC Arkusz danych(PDF) 15 Page - STMicroelectronics