EB632 datasheet(24/112 Pages) FREESCALE

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Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2

Freescale Semiconductor

HDI16

HM/HDM

9–10

Host Mode/Host DMA Mode

When host DMA mode is enabled, if HCR[HICR] is set, the HREQ pin requests DMA transfers, the TREQ and RREQ bits

select the direction of DMA transfers, and the HACK input pin is used as a DMA transfer acknowledge input, if OAE in HPCR

is cleared. If the DMA direction is from core to host, the contents of the selected register are written to the host data bus when

HACK is asserted. If the DMA direction is from host to core, the selected register is read from the host data bus when HACK

is asserted.

If HPCR[OAE] is set, a host read or write to host address 0x4 is used as a DMA transfer acknowledge. If the DMA direction is

from core to host, the contents of the selected register are written to the host data bus when the host reads from host address

0x4. If the DMA direction is from host to core, the selected register is read from the host data bus when the host writes to host

address 0x4.

HM also controls the size of the DMA word to be transferred. The HDI16 data register selected during a host DMA transfer is

determined by a 2-bit address counter, which is preloaded with the value in HM. The address counter replaces the HA[0–1]

bits of the HDI16 during a host DMA transfer. The address counter can be initialized with the INIT bit feature. After each DMA

transfer on the host data bus, the address counter is decremented. When the address counter reaches the last register, the

address counter is loaded with the value in HM.

Thus, 16-bit, 32-bit, 48-bit, or 64-bit data can be transferred in a circular fashion, and the need is eliminated for the DMA

controller to supply the HA0–2] pins (HPCR bit OAE=0) or to read/write at host address 0x4 (HPCR bit OAE=1). For 32-, 48-

or 64-bit data transfers, the core CPU interrupt rate is reduced by a factor of 2, 3, or 4, respectively, from the host request

rate. That is, for every two or three host processor data transfers of one byte each, there is only one 64-bit core CPU interrupt.

This bit is available only in ICR mode (HCR[HICR] = 1).

When the HDI16 is in ICR priority non-DMA mode (the HPCR[DMA] bit is cleared and HCR[HICR] is set), data transfer size is

defined by HM, as described in Table 22. The transfer size causes the RX

x/TXx register read/write at the last (trigger)

address to clear the RXDF/TXDE bits, respectively.

HF2

Host Flag 2

A general-purpose flag for host-to-core communication. The host processor can set or clear HF2. HF2 is reflected in the HSR

on the core side of the HDI16.

HF3

Host Flag 3

A general-purpose flag for host-to-core communication. The host processor can set or clear HF3. HF3 is reflected in the HSR

on the core side of the HDI16.

HDRQ

HREQ/HTRQ and HACK/HRRQ Pin Control

Controls the HREQ/HTRQ and HACK/HRRQ pins. If HDRQ is cleared, the HREQ/HTRQ pin functions as a single HREQ. If

HDRQ is set, the HREQ/HTRQ and HACK/HRRQ pins function as HTRQ and HRRQ, respectively. This bit is available only in

non-DMA (interrupt) mode (HPCR[DMA] = 0).

TREQ/HDM0

HREQ/HTREQ Pin Control

Controls the HREQ/HTREQ pin for host transmit data transfers. In non-DMA (interrupt) mode (DMA = 0 in the HPCR), TREQ

enables host requests via the host request (HREQ or HTRQ) pin when the Transmit Data Register Empty (TXDE) status bit in

the ISR is set. If TREQ is cleared, TXDE interrupts are disabled. If TREQ and TXDE are set, the host request pin is asserted.

In DMA modes (HPCR[DMA] = 1 and HCR[HICR] = 1), software must set or clear TREQ to select the direction of DMA

transfers. Setting TREQ sets the direction of the DMA transfers as host-to-core and enables the HREQ pin to request data

transfers.

When HCR[HICR] is cleared and HPCR[DMA] is set, a TREQ read reflects the status of NOT HDM0 in HCR. When written,

TREQ affects the INIT mode. See Table 20.

RREQ/HDM0

HREQ and HRREQ Pin Control

Controls the HREQ and HRREQ pins for host receive data transfers. In non-DMA (interrupt) mode (HPCR[DMA] = 0), RREQ

enables host requests via the host request (HREQ or HRRQ) pin when the Receive Data Register Full (RXDF) status bit in

the ISR is set. If RREQ is cleared, ISR[RXDF] interrupts are disabled. If RREQ is set, the host request pin (HREQ or HRRQ)

is asserted if ISR[RXDF] is set.

In host DMA mode (DMA = 1 in the HPCR and HICR = 1 in the HCR), RREQ must be set or cleared by software to select the

direction of DMA transfers. Setting RREQ sets the direction of the host DMA transfers to core-to-host and enables the HREQ

pin to request data transfers. When HICR in HCR is cleared and DMA in HPCR is set, RREQ, when read, reflects the status

of HDM0 in HCR.

When HCR[HICR] is cleared and HPCR[DMA] is cleared, an RREQ read reflects the status of HCR[HDM0]. When written,

RREQ affects the INIT mode. See Table 20.

Table 17. Mask Set 2K42A ICR Bit Descriptions (Continued)

Name

Description

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