EB632 datasheet(73/112 Pages) FREESCALE

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Errata

Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2

Freescale Semiconductor

CPM37

Requirement for Software to Disable FCC After Error

Date Added: 5/30/2000

Description: There are four errors in the FCC transmitter that require software to disable and en-

able the transmitter before it can continue to operate correctly. The four errors are:

CTS-LOST indication in the HDLC transmitter

Late collision in the fast ethernet transmitter

Underrun in any of the FCC transmitter protocols

Expiration of RL in fast ethernet

Workaround: None available.

System Number: 4040, 3980, 2314

Fix Plan: Specification was changed to include details for error handling software.

0K40A

1K42A

2K42A

2K87M

Table 50. 2K87M Errata

Errata

Number

Errata Description

Applies

to Mask

SIU13

SDAMUX not Valid in Single-MSC8103 Mode

Date Added: 3/14/2002

Description: SDAMUX

signal is disabled (stuck at ’0’) when SDRAM machine handles the

memory access and the chip is programmed to single-MSC8103 mode (BCR[EBM]=0).

Workaround: None.

0K40A

1K42A

2K42A

2K87M

SIU16

Bus Busy Disable Mode Can Hang 60X Bus in Multi-Master Systems

Date Added: 5/21/2002

Description: The bus busy disable mode (SIUMCR[BBD=1]) can not be used if the MSC8103

is not the only master on the 60x-compatible bus. Using this mode in such a system can cause the

60x-compatible bus to hang.

Workaround:

If the external master supports the ABB signal, do not use the bus busy disable mode and

connect this signal to the MSC8103. The DBB signal can either be connected or can be

pulled up.

If the external master does not support the ABB signal do one of the following:

a. Do not use the bus busy disable mode and generate the ABB signal

externally. The DBB signal can either be connected or can be pulled up.

The following external ABB implementation should be sufficient to work

around the problem: Assert the ABB signal whenever a qualified bus

grant for the external master is sampled (Bus grant asserted while

ARTRY

and ABB are deasserted). Deassert the ABB signal when there is

no qualified bus grant. The deassertion of ABB should be as follows:

Drive ABB to VDD for half a clock cycle and then stop driving it (high

impedance).

b. If using the internal arbiter and up to two external masters, connect the

external bus grants (through an AND gate if more than one) to an

available external bus request and define the priority for that request to

be the highest in the PPC_ALRH register. The DBB signal can either be

connected or can be pulled up.

Fix Plan: TBD

2K87M

Table 49. Errata Resolved by Specification Change in Mask Set 2K87M (Continued)

Errata

Number

Errata Description

Applies

to Mask

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