EB632 datasheet(52/112 Pages) FREESCALE

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Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2

Freescale Semiconductor

CPM

14.4.21 Programming and Operating the TC Layer

The host should first program the mode registers of each TC block to be active, according to the number of TC

channels required. Then, FCC2 is programmed to work on the UTOPIA interface with the active TC blocks.

Finally, FCC2 and the PHYs of the TC channels are enabled. The transmit channels for each TC block are enabled

by setting TCMODEx[TXEN]. The receive channels for each TC block are enabled by setting TCMODEx[RXEN].

The host polls the CD bits of each enabled TC block to verify that its receive cell delineation state machines are

synchronized. For every TC block that is synchronized, the host clears the CDT bit in its event register. When all

the enabled TC blocks are synchronized, the host terminates its initialization routine, and the system starts normal

operation.

When a TC block gets out of synchronization, the corresponding TCGSR[CD] is cleared. This change causes a

TCER[CDT] interrupt to the host (if enabled).

On the receive path, the TC performs the following functions:

Receives the bit stream via the SI.

Attempts to gain synchronization on the ATM cell boundaries by checking each byte (HEC candidate) against

the HEC calculated on the preceding 32 bits (ATM cell header candidate).

Once synchronized, performs the descrambling function on the cell payload (if enabled), performs the coset

function on the HEC (if enabled), checks for HEC errors and corrects single HEC errors when found (again, if

enabled). Cells containing multi-bit header errors (at least 2 errors) are discarded. Idle and unassigned cells are

filtered (discarded) when detected (if the filters are enabled). Once a cell is processed, it passes to the TC

receive FIFO, and the internal TC cell counters are updated. The cell is passed from the TC receive FIFO via

the UTOPIA interface to the FCC2 receive FIFO.

An overrun condition occurs when the TC receive FIFO is full, the CP is busy, and the FCC cannot read a cell from

it via the UTOPIA interface before another valid cell is received. The incoming cell is discarded and TCER[OR]

interrupt is sent to the host (if enabled).

On the transmit path, once enabled, the TC performs the following functions:

Starts requesting for cells to send via the UTOPIA interface.

When a cell is passed via the UTOPIA interface to the TC transmit block, it is stored in the TC transmit FIFO.

When a cell is to be sent, it is read from the TC transmit FIFO and is processed. The scrambling function is

performed on its payload (if enabled), its header HEC value is calculated and the coset function is performed

on the HEC (if enabled).

The cell is then sent to the PHY via the SI. Once the cell transmission is complete, the relevant TC cell counters

are updated.

An underrun condition occurs when a cell is to be sent to maintain the bit rate, but the TC transmit FIFO is empty.

An idle cell is sent instead. This condition generates a TCER[UR] interrupt (if not masked) if TCMODE[URE] is

set. When a TC cell counter overflows, an interrupt is set (if enabled).

A TC channel provides the data rate dictated by the PMD device by operating the FCC2 in one of two modes:

•

External Rate. In this mode, the external device determines the data rate. The CP keeps the FCC FIFO full by

inserting ATM cells or idle cells (if ATM cells are not available) into the FCC FIFO whenever it is not full.

This operation ensures that the cell stream is the data rate required by the PMD. In general, the TC transmit

FIFO is never empty, and thus would not need to generate idle cells. However, if the CP is busy, and the TC is

forced to generate an idle cell because its transmit FIFO is empty, an underrun condition occurs. The UR

interrupt is sent to the host (if not masked) if TCMODE[URE] is set. See Figure 23. This mode generates a

greater CP load than the internal rate mode.

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