LP3972 datasheet(20/59 Pages) NSC

20 / 59 page

Buck Converter Operation (Continued)

SOFT START

The buck converter has a soft-start circuit that limits in-rush

current during start-up. During start-up the switch current

limit is increased in steps. Soft start is activated only if EN

goes from logic low to logic high after V

IN reaches 2.7V. Soft

start is implemented by increasing switch current limit in

steps of 213 mA, 425 mA, 850 mA and 1700 mA (typ. Switch

current limit). The start-up time thereby depends on the

output capacitor and load current demanded at start-up.

Typical start-up times with 10 µF output capacitor and 1000

mA load current is 390 µs and with 1 mA load current

its 295 µs.

LDO - LOW DROP OUT OPERATION

The LP3672 can operate at 100% duty cycle (no switching;

PMOS switch completely on) for low drop out support of the

output voltage. In this way the output voltage will be con-

trolled down to the lowest possible input voltage. When the

device operates near 100% duty cycle, output voltage ripple

is approximately 25 mV. The minimum input voltage needed

to support the output voltage is

IN, MIN =ILOAD *(RDSON, PFET +RINDUCTOR)+VOUT

• I

LOAD

Load Current

• R

DSON, PFET

Drain to source resistance of PFET

switch in the triode region

• R

INDUCTOR

Inductor resistance

SPREAD SPECTRUM FEATURE

Periodic switching in the buck regulator is inherently a

noisier function block compared to an LDO. It can be chal-

lenging in some critical applications to comply with stringent

regulatory standards or simply to minimize interference to

sensitive circuits in space limited portable systems. The

regulator’s switching frequency and harmonics can cause

“noise” in the signal spectrum. The magnitude of this noise is

measured by its power spectral density. The power spectral

density of the switching frequency, F

C, is one parameter that

system designers want to be as low as practical to reduce

interference to the environment and subsystems within their

products. The LP3972 has a user selectable function on

chip, wherein a noise reduction technique known as “spread

spectrum” can be employed to ease customer’s design and

production issues.

The principle behind spread spectrum is to modulate the

switching frequency slightly and slowly, and spread the sig-

nal frequency over a broader bandwidth. Thus, its power

spectral density becomes attenuated, and the associated

interference electro-magnetic energy is reduced. The clock

used to modulate the LP3972 buck regulator can be used as

a spread spectrum clock via 2 I

2C control register (System

Control Register 1 (SCR1) 8h’80) bits bk_ssen, and slomod.

With this feature enabled, the intense energy of the clock

frequency can be spread across a small band of frequencies

in the neighborhood of the center frequency. The results in a

reduction of the peak energy!

The LP3972 spread spectrum clock uses a triangular modu-

lation profile with equal rise and fall slopes. The modulation

has the following characteristics:

•

The center frequency:

C = 2 MHz, and

•

The modulating frequency,

M = 6.8 kHz or 12 kHz.

•

Peak frequency deviation:

∆_f = ±100 kHz (or ±5%)

•

Modulation index

β = ∆_f/f

M = 14.7 or 8.3

Switching Energy RBW = 300 Hz

20207641

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